In verifying programs for embedded systems,
it is essential to reduce the verification time
because state explosion may occur in model checking.
One solution is to reduce the number of interrupt handler execution.
In particular, when periodic interrupts such as timer interrupts are incorporated, it is necessary to know the physical time.
In this paper, we define a control flow automata (CFA) that can handle time
and propose an algorithm based on interrupt handler execution reduction (IHER).
The proposed method reduces the number of interrupt executions,
including timer interrupts.
A case study verifies the effectiveness of this algorithm.