Version 1
: Received: 6 May 2024 / Approved: 6 May 2024 / Online: 6 May 2024 (10:33:14 CEST)
How to cite:
Emon, M. Z. A.; Salim, K. M.; Chowdhury, M. I. B. Design and Analysis of a High Gain, Low-Noise and Low-Power Analog Front End for ECG Acquisition in 45nm Technology Using Gm/Id Method. Preprints2024, 2024050289. https://doi.org/10.20944/preprints202405.0289.v1
Emon, M. Z. A.; Salim, K. M.; Chowdhury, M. I. B. Design and Analysis of a High Gain, Low-Noise and Low-Power Analog Front End for ECG Acquisition in 45nm Technology Using Gm/Id Method. Preprints 2024, 2024050289. https://doi.org/10.20944/preprints202405.0289.v1
Emon, M. Z. A.; Salim, K. M.; Chowdhury, M. I. B. Design and Analysis of a High Gain, Low-Noise and Low-Power Analog Front End for ECG Acquisition in 45nm Technology Using Gm/Id Method. Preprints2024, 2024050289. https://doi.org/10.20944/preprints202405.0289.v1
APA Style
Emon, M. Z. A., Salim, K. M., & Chowdhury, M. I. B. (2024). Design and Analysis of a High Gain, Low-Noise and Low-Power Analog Front End for ECG Acquisition in 45nm Technology Using Gm/Id Method. Preprints. https://doi.org/10.20944/preprints202405.0289.v1
Chicago/Turabian Style
Emon, M. Z. A., Khosru Mohammad Salim and Md. Iqbal Bahar Chowdhury. 2024 "Design and Analysis of a High Gain, Low-Noise and Low-Power Analog Front End for ECG Acquisition in 45nm Technology Using Gm/Id Method" Preprints. https://doi.org/10.20944/preprints202405.0289.v1
Abstract
In this work, an analog front-end (AFE) circuit for Electrocardiogram (ECG) detection system has been designed, implemented, and investigated in an industry-standard Cadence simulation framework using advanced technology node of 45 nm. The AFE consists of an instrumentation amplifier, a Butterworth band-pass filter (with fifth-order low-pass and second-order high-pass sections), and a second-order notch filter- all are based on two-stage, Miller-compensated operational transconductance amplifiers (OTA). The OTAs have been designed employing the $g_m/I_D$ methodology. Both the pre-layout and post-layout simulation were carried out. The layout consumes an area of 0.0058 mm$^2$ without the resistors and capacitors. Analysis of various simulation results were carried out for the proposed AFE. The circuit demonstrates a post-layout bandwidth of 239 Hz with a variable gain between 44 to 58 dB, a notch depth of -56.4 dB at 50.1 Hz, a total harmonic distortion (THD) of -59.65 dB (less than 1\%), an input referred noise spectral density of $
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
