1. Introduction

Figure 1. (a) DAB circuit diagram (b) Lossless AC equivalent circuit diagram.

Figure 1. (a) DAB circuit diagram (b) Lossless AC equivalent circuit diagram.

2. Basic operating principle of DAB using conventional phase shift, Dual phase, and Extended phase shift control.

Figure 2. (a) DAB waveforms for (a) CPS (b) EPS (c) DPS for condition $0\le D_2\le D_1\le 1$ (d) DPS for condition $0\le D_1\le D_2\le 1$.

Figure 2. (a) DAB waveforms for (a) CPS (b) EPS (c) DPS for condition $0\le D_2\le D_1\le 1$ (d) DPS for condition $0\le D_1\le D_2\le 1$.

Figure 3. Power characteristics under (a) CPS (b) EPS (c) DPS.

Figure 3. Power characteristics under (a) CPS (b) EPS (c) DPS.

From the voltages and current waveforms of Figure 2(a), the expression for the current for the first half-cycle by assuming, t₀=0, t₁=DT_h and t₂=T_h is given by:

(1)

Where, f_s is the switching frequency and L_tot is the total inductance.

Therefore, the equation for the output power under CPS control can be written as:

(2)

EPS and DPS control were introduced to overcome some of the limitations of CPS modulation. The aim of these switching patterns is to extend soft switching region and minimise/ exclude the reactive power circulating within the converter bridges, thereby improving overall efficiency of the converter. With EPS control, additional inner parameter, D₁ which is the phase shift between the legs of one H-bridge is introduced, while in H- bridge two, the cross connected switches are switched simultaneously. This results in a quasi-square AC output waveform for the bridge where inner shift D₁ is used and a full AC square waveform for the second H- bridge as Figure 2 (b) depicts. D₁ is the parameter used to extend the ZVS and reduce the reactive power. The phase shift D₂, is the outer phase shift angle that controls the power flow magnitude and direction, which is equivalent to D in CPS modulation.

(3)

Thus, average power when EPS modulation is used, can be obtained as

(4)

DPS control aims to address some of these limitations by not restricting one of the AC link voltages to a full square wave operation, but rather, zero states are introduced for both H-bridges, unlike EPS control, in addition to enhancing the regulation flexibility further. This is achieved by additional inner phase shift between both the converter switch pairs S₁-S₃ and Q₁-Q₃ (leg 1 and leg 2 of bridge A and Leg 1 and 2 of bridge B). Figure 2 (c) and (d), illustrates the resulting waveforms under DPS control. D₁ is the inner phase shift for both H-bridges and D₂ is the external phase shift (D₂=D in CPS control). The resulting waveforms when DPS control is applied can be divided into two operating conditions, which are:

(5)

When,

The current expression of each segment for the first half cycle is derived by assuming t₀=0, t₀=0, t₁= D₂T_h, t₂= D₁T_h and t₃= T_h:

(6)

From (6), the ideal power transferred by the converter is given for this condition as

(7)

(8)

Similar analysis can be performed for the second operating condition in (5). By assuming, t₁=(D₂+D₁-1)T_h, t₂=D₁T_h, t₃= D₂T_h and t₄=T_h . Therefore, current expression of each segment for the first half cycle is:

(9)

The ideal power for this condition is also computed as:

(10)

(11)

2. Basic operating principle of DAB using TPS Control

Figure 3. (a) DAB circuit diagram (b) Switches turn on/turn off signals and ideal voltage/current waveforms under TPS scheme.

Figure 3. (a) DAB circuit diagram (b) Switches turn on/turn off signals and ideal voltage/current waveforms under TPS scheme.

2.1. TPS Modes of operation 

Based on all possible combinations of phase shifts D₁, D₂ and D₃; full, partial and no overlaps of both transformer terminal voltage waveforms, give rise to six different switching modes for forward power flow, and their complements for reverse power flow. Importantly it’s the modes boundaries that set the number of TPS modes. In this section, a comprehensive analysis of the converter performance indices will be performed for each mode. TPS control involves different operating modes, in addition to loading condition (whether the converter is lightly or heavily loaded).

In the analysis, the following assumptions are made:

-

Lossless DAB converter.

-

Fixed V_DC1 & V_DC2 DC link voltages.

-

Buck mode operation (V_DC1>nV_DC2), boost mode operation (V_DC1<nV_DC2) is similar to buck mode and will be omitted in this chapter.

-

The turn’s ratio of the transformer is n and f_s is the switching frequency.

-

The transformer magnetising inductance is neglected.

-

The H-bridge B is referred to the primary side, while the transformer leakage inductance is added to external inductor, resulting in a total inductance L_tot.

-

Other short time scale factors such as switching dynamics and dead band effects are also neglected.

a) 

Modes 1 and 1’

Ideal operating waveforms of the modes are depicted in Figure 4. Mode 1 shown in Figure 4 (a), is characterised by a full positive-half-cycle overlap of both bridges terminal voltages with D₁≥D₂, while complimentary mode 1’ waveforms, in Figure 4 (b), are graphically described by full overlap of positive and negative half cycles of AC link voltages with bridge B waveform being shifted by 180⁰, to reverse the converter operation resulting in equal but negative power. The remaining part of this section performs derivation of several key performance indicators for each of the following operating mode.

Figure 4. Steady state voltage/current waveforms for (a) Mode 1 (b) Mode 1’.

Figure 4. Steady state voltage/current waveforms for (a) Mode 1 (b) Mode 1’.

i. 

Mode 1

The mode boundary conditions should ensure that full overlap of both bridge AC voltages is strictly maintained. Thus, by observing Figure 4 (a), the following two constraints are defined,

(12)

Inductor current, is crucial for active and reactive power calculations. Thus, applying Kirchhoff voltage law (KVL) in the equivalent circuit diagram of Figure 1 (b), the analytical expression for the current can be written as

(13)

Where t_n represents n^th switching instant, $v_{ac1}\left(t\right)$ is the coupling transformer primary voltage and $v{{}^{\prime }}_{ac2}(t)$ is the secondary transformer voltage referred to the primary side. According to Figure 4 (a), nine different switching segments emerge that will completely be analysed for this mode.

Interval t₀ - t₁: Figure 5 (a) shows the equivalent circuit during this switching instant. Since the current is negative; i_L, flows through freewheeling diodes D_S1 and D_S4 in bridge A due to positive bridge A output voltage. For bridge B, diode D_Q1 and switch Q₃ conduct the current. The inductor voltage is clamped at V_DC1. Therefore, the current is expressed by,

(14)

Interval t₁ – t₁’: The polarity of inductor current changes from negative to positive at t₁^’. In bridge A, the current flows through switches S₁ and S_4, while for bridge B, the current flows through D_Q1 and Q₃. The current remains the same as in previous switching instant while continuing to increment. The voltage across the coupling inductor is V_DC1. This is depicted in Figure 5 (b).

Interval t₁’ - t₂: The equivalent circuit for this segment is shown in Figure 5 (c). Since it is assumed that converter works in buck mode where V_DC1>nV_DC2, therefore current slope is increasing. With both bridges output voltage been positive and a positive inductor current polarity, switches S₁ and S₂ of bridge A remain on. In bridge B, i_L, flows through the reverse recovery diodes, D_Q1 and D_Q4.The resultant voltage across the inductor is V_DC1-nV_DC2, thus, the inductor current is given by,

(15)

Interval t₂ - t₃: S₁ and S₂ of bridge A are still conducting. In secondary bridge B, current flows through Q₂ and D_Q4 as illustrated in Figure 5 (d). The voltage impressed across inductor is V_DC1, thus, current through L_tot can be expressed as

(16)

Interval t₃ - t₄: Both bridge A and bridge B voltages are zero and Figure 5 (e), depicts, the equivalent circuit. The inductor current remains unchanged and circulates in D_S2, S₄, Q₂ and D_Q4 of both bridges. The voltage across the inductor is zero and thus, the inductor current is

(17)

Interval t₄ - t₄’: Figure 5 (f) shows the equivalent circuit for this duration. Switch S₄ of bridge A is turned off and the current flows through the diagonal anti-parallel diodes D_S2 and D_S3 since bridge A voltage is negative. The status of bridge B remains unchanged, where i_L, decreases linearly and is carried by Q₂ and D_Q4. Voltage across the inductor is - V_DC1. Thus,

(18)

Interval t₄’ - t₅: The inductor current polarity changes S₂ and S₃ of bridge A freewheel. In bridge B i_L, flows through D_Q2 and Q₄. The equivalent circuit structure is shown in Figure 5 (g). The inductor voltage remains at -V_DC1 and the value of inductor current is given by expression (18).

Interval t₅ - t₆: During this sub-period, S₂ and S₃ of bridge A are still on, while D_Q2 and D_Q3 conduct for bridge B as Fig.5 (h) demonstrates. The inductor voltage is V_DC1+nV_DC2. Thus, the inductor current is

(19)

Interval t₆ - t₇: The switching pattern for this sub-period is similar to previous segment t₅-t₆ and equivalent circuit diagram showing the current path is displayed Figure 5 (i). S₂ and S₃ of

Figure 5. Mode 1 equivalent circuits sub-periods for inductor current (a) t_o-t₁ (b) t₁- t₁^’ (c) t₁^’-t₂ (d) t₂- t₃ (e) t₃- t₄ (f) t₄- t₄^’ (g) t₄^’ _- t₅ (h) t_5- t₆ (i) t_6- t₇ (i) t_7- t_8.

Figure 5. Mode 1 equivalent circuits sub-periods for inductor current (a) t_o-t₁ (b) t₁- t₁^’ (c) t₁^’-t₂ (d) t₂- t₃ (e) t₃- t₄ (f) t₄- t₄^’ (g) t₄^’ _- t₅ (h) t_5- t₆ (i) t_6- t₇ (i) t_7- t_8.

bridge A continue to conduct. For bridge B switch Q₁ and D_Q3 conduct. The voltage across the inductor is -V_DC1. Therefore, the inductor current is,

(20)

Interval t₇ - t₈: Bridge A and bridge B voltages are both zero and thus, the voltage across the inductor is likewise zero as demonstrated by Figure 5 (j). For both H-bridges, S₂, D_S4, D_Q2 and Q₄ conduct respectively. The inductor current during this sub-period is

(21)

Since the average value of the inductor current i_L(t) for one complete cycle (T_s), has to be zero, it is therefore only necessary to compute the current for the first half cycle. Moreover, due to half-wave symmetry of the inductor current waveform, it can be shown that,

(22)

Considering the volts-second balance of the inductor current, initial inductor current, i_L(t_o), can be derived from equations (14) to (17), by assuming, t_n values of, t₀=0, t’₁=D₃T_h, t₂=(D₃+ D₂)T_h, t₃=D₁T_h and t₄=T_h . Where, T_h=T_s/2.

(23)

Substituting values of t_n, in the expression (23) above, $i_L\left(t_0\right)$ can be obtained

(24)

From (24), the currents for each switching interval can be derived as,

(25)

(26)

(27)

(28)

The peak current for this mode of operation is given by

(29)

The rms current can be expressed as follows:

(30)

Inserting t₀=0, t₁=D₃T_h, t₂=(D₃+ D₂)T_h, t₃=D₁T_h ,t₄=T_h in (3.19) and rearranging yields,

(31)

Based on the derived expressions, derivations for active power, reactive power, and ZVS operation possibility for each switch and its range are presented below.

Average power transferred by the converter can be calculated at either bridge, by considering the assumptions made previously,

(32)

The transmitted power is obtained as,

(33)

Simplifying and rearranging expression (3.22) results in,

(34)

After inserting t_n values and further manipulation of (34), mode 1 active power equation can be derived as

(35)

From (35), range of power transfer can be determined, in order to characterise mode upper and lower power operation limits. This is performed by first normalising the power equation with respect to maximum power achievable by the converter. This base power is obtained through CPS equation (2) of previous chapter, when external phase shift D=0.5.

(36)

Thus,

(37)

The maximum and minimum power transfer in per unit and corresponding maximum and minimum TPS control values can be obtained by solving a basic optimisation problem for the normalized power formula (37) and applying the mode operational constraints (12). The required steps to determine these parameters is summarised by flow chart of Figure 6. Results obtained from this are:

(38)

Figure 6. Steps required to establish maximum and minimum power range.

Figure 6. Steps required to establish maximum and minimum power range.

Reactive power is a parameter of interest to investigate in DAB converter, since by reducing reactive power consumption; RMS inductor current is minimised for a specified level of power transfer. This reduces conduction and copper losses. In this paper, reactive power is calculated by computing the apparent power S_L at the inductor. Since inductors do not absorb active power, the apparent power is therefore equivalent to the reactive power consumption by the inductor. This is, by definition equivalent to the total reactive power consumption at the converter H-bridges. Hence, reactive power Q, can be defined by,

(39)

Equation for mode 1 RMS current is denoted in (31). The RMS value for the inductor voltage can be calculated by referring to Figure 4 (a),

(40)

Substituting t_n values into (40), mode 1 RMS voltage is

(41)

By, merging equations (31) and (41), a more accurate definition of DAB true reactive power emerges

(42)

Assuming IGBT switches, in order to ensure that the converter switches are operating with zero voltage switching (ZVS), anti-parallel diodes must conduct prior to switch turn on. After switch voltage drops to zero, current commutates from the anti-parallel diode to the switch enabling turn on at zero voltage, resulting in zero turn on power loss.Thus , at the instant of switch turn on, current in the switch must be negative. This provides the condition for ZVS. With respect to the switches in Figure 1 (a) and their respective conducting current directions, conditions for the switches ZVS can be summarised as

(43)

-

Generation of inequality for each switch, by observing the instant the switch starts to conduct first.

(44)

-

Summarise inequalities of expression (44) by removing redundant expressions and check if the inequality doesn’t contradict the current waveform.

(45)

• By mapping (45) to the respective segments of the inductor current of Figure 3 (a), inequality $i_L\left(t_2\right)<0$ introduces a conflict and hence, for this mode, it can be concluded that soft switching is not possible for all DAB converter switches.Note that, this is applicable when the voltage conversion ratio $\frac{n{V}_{DC2}}{V_{DC1}}<0$. When,$\frac{n{V}_{DC2}}{V_{DC1}}>0$, the resulting condition might be different.

i. 

Mode 1’

Mode1’ is essentially the mode generating equal power in magnitude to mode 1 but in reverse direction. Hence, bridge B voltage waveform is shifted by 180°. Therefore, the boundary condition is defined by full overlap of positive and negative half cycles of the bridges AC voltage waveforms as Figure 4 (b) depicts. The same methodology can be adapted to derive the mode constraint as in previous mode and by extending the mode voltage waveforms to the negative half plane, it can be concluded that the following mode 1’constraints have to be maintained,

(50)

Analysis for various switching instants of the inductor current is performed prior to deriving key parameters. Nine distinct segments emerge as illustrated in the Figure 4 (b). The second half cycle operation is similar, but with inverted inductor current and complimentary switches conducting, the equivalent circuit and steady state value of the inductor current for the first half period is defined for convenience and this will, likewise, also be the case for all the remaining operating modes.

Interval t₀ - t₁: The inductor current is negative during this switching state and the resulting equivalent circuit is demonstrated by Figure 7 (a). Switches S₁ and S₄, are in the direct conduction path, the current free wheels through integrated anti-parallel diodes D_S1 and D_S4 for Bridge A. While for Bridge B, the current flows through D_Q2 and Q₄ respectively. The voltage across the inductor is V_DC1. Inductor current is given by

(51)

Interval t₁ - t₁’: Figure 7 (b) depicts the equivalent circuit for this time segment. In bridge A, i_L flows through diodes D_S1 and D_S4. Similarly, the current in bridge B freewheels through reverse recovery diodes D_Q2 and D_Q3.Inductor voltage is clamped at V_DC1+nV_DC2.

(52)

Interval t₁’- t₂: Current polarity reverses for this time duration, whilst linearly increasing, plotted by circuit diagram of Figure 3.6 (c). Switches S₁ and S₄ of bridge A are condu cting, while in Bridge B the current flows through Q₂ and Q₃. Inductor voltage is still clamped at V_DC1+nV_DC2. The current is similarly given by (52). The interval ends upon Q₂ turn off.

Figure 7. Mode 1’ equivalent circuits sub-periods for inductor current (a) t_o-t₁ (b) t₁-t’₁ (c) t’_{1 -}t₂ (d) t₂- t₃ (e) t₃- t₄ .

Figure 7. Mode 1’ equivalent circuits sub-periods for inductor current (a) t_o-t₁ (b) t₁-t’₁ (c) t’_{1 -}t₂ (d) t₂- t₃ (e) t₃- t₄ .

Interval t₂ - t₃: Figure 7 (d), demonstrates the equivalent circuit showing the current path during this duration. For bridge A, the same switches continue to conduct as in previous segment, while in bridge B the current freewheels in diode D_Q1 and flows through switch Q₃. The inductor voltage is V_DC1. Inductor current for this segment can be written as

(53)

Interval t₃ – t₄: The schematic circuit showing the current path during this time instant is displayed in Figure 3.6 (e). Both bridge terminal voltages are zero and thus no power is transferred. The current circulates through D_S1 and S₄, in bridge A. For bridge B the current path remains the same as in previous interval. The inductor current slope is zero and thus, its value is given by (3.38).

By substituting, t_n values of, t₀=0, t₁=(1-|D₃|)T_h, t₂=(1-|D₃|+ D₂)T_h, t₃=D₁T_h and t₄=T_h, one can evaluate expressions comprising the inductor current at various switching instant, peak current, , RMS current, along with, the average power, reactive power and ZVS constraints,

Table 1. Key expressions for Mode 1’.

Table 1. Key expressions for Mode 1’.

following similar steps outlined in mode 1. To reduce the number of equations, the final derivation of this expressions is summarized in Table 1.

According to the results obtained, it can be observed in Table 1 that mode peak current is given by i_L(t₃). The derived per unit values for upper and lower mode active power limits which is ±0.5 pu, is also evaluated by applying a similar optimization problem procedure as in mode 1, while decrementing D₃ from 0 to -1 (rather than incrementing). The corresponding TPS modulation parameters that achieve these limits are also tabulated. By also taking a similar approach for determination of ZVS, as in mode 1, soft switching operation is possible for all the switches as long as the ZVS constraint given in Table 3.1, are satisfied.

Even though, the obtained mode steady state equations look dissimilar to previous derivations defined for mode 1, it can be shown that by substituting |D₃|= 1- D₃, in expressions of mode1’, results in inverted but identical equations of mode 1, which verifies the complementary nature of this mode, compared to mode 1.

All other remaining modes of operations 2 to 6 and their respective complements, which are graphically represented in Figure 8, are analysed in Appendix A, following similar procedure as in preceding TPS modes above.

Figure 8. Remaining modes steady state voltages and current (a) Mode 2 (b) Mode 2’(c) Mode3 (d) Mode 3’ (e) Mode 4 (f) Mode 4’(g) Mode 5 (g) Mode 5’ (h) Mode 6 (i) Mode 6’.

Figure 8. Remaining modes steady state voltages and current (a) Mode 2 (b) Mode 2’(c) Mode3 (d) Mode 3’ (e) Mode 4 (f) Mode 4’(g) Mode 5 (g) Mode 5’ (h) Mode 6 (i) Mode 6’.

Normalised inductor currents to (1/4f_sL), for the positive half cycle switching instants are derived and listed for the remaining modes in Table II (where f_s is the switching frequency). Detailed derivation of the currents for each mode can be found in the appendix. Due to inductor current half-wave symmetry, negative half cycle values are omitted. These can be calculated by counter positive half cycle values.

The per unit average power normalised to maximum power transferred by the converter is listed in Table 3 for the remaining modes. The base power used is obtained with CPS modulation at 90⁰ phase shift between the two half bridge voltages.

(54)

Range of power transfer for each mode is also computed to characterise mode limits, by applying the mode operational constraints to the computed power equations. This shows the converter, power transfer, capability with respect to the full range under specific mode of operation. In complementary modes, bridge 2 waveform is shifted by 180⁰ from non-complimentary mode, hence resulting in the exact but negative power range. From Table 3, it can be seen that modes 6 and 6’ are the only modes that cover the whole converter operating power range.

Modes 1, 1’, 2 and 2’are capable of charging and discharging operation, but only for half the power range. Modes 3, 4, 5 and 6 with their complements only provide unidirectional power transfer capability each. Finally, it is worth noting that, in mode 3 and 3’ power transfer is independent of D₃, meaning that it can be solely controlled by controlling bridge voltages. The ZVS constraints are derived and also listed in Table 4. Only modes where ZVS is realisable for all switches are indicated with their constraints. Otherwise ZVS is only partially obtained for the converter, i.e., for some switches only as indicated by modes 1, 3, 3’ and 5. The, RMS current, RMS voltage and and the reactive power for the remaining modes are listed in Table 4.

Table 2. Inductor currents (i_L) for positive half cycle switching intervals normalized to $1/4f_{s}L$.

Table 2. Inductor currents (i_L) for positive half cycle switching intervals normalized to $1/4f_{s}L$.

Table 3. Remaining DAB modes of operation & power equations using TPS control.

Table 3. Remaining DAB modes of operation & power equations using TPS control.

Table 4. ZVS constraints, RMS currents and reactive power for the remaining modes.

Table 4. ZVS constraints, RMS currents and reactive power for the remaining modes.

3. Generalization of TPS control scheme

i. 

Conventional phase shift (CPS): This is defined by D₁=1, D₂=1. Applying this definition to modes 6 and 6’ yields 0≤D₃≤1. CPS is therefore fully achieved with these two modes.

ii. 

Dual phase shift (DPS): This is characterized by D₁=D₂=D. Applying this definition to modes 6 and 6’ yields D≥0.5 and 1-D≤D₃≤D. This does not represent the complete control range for D. Considering modes 3 and 3’, if D₁=D₂=D, therefore D≤0.5 and D≤D₃≤1-D. Consequently, modes 3, 3’, 6 and 6’ can cover the whole operating range for DPS.

iii. 

Extended phase shift (EPS): This is defined by either bridge voltage being a full square wave with the other bridge voltage controlled to be a quasi-square wave. Considering modes 6 and 6’, if

- 

D₁=1, therefore D₂≥0 and 1-D₂≤D₃≤1

- 

D₂=1, therefore D₁≥0 and 0≤D₃≤D₁

4. Optimization example using reactive power minimization algorithm

Figure 9. Map of TPS modes vs output power ranges in pu.

Figure 9. Map of TPS modes vs output power ranges in pu.

In this reactive power optimization algorithm, The first step is to convert all modes derived peak current, RMS currents, RMS voltages, active and reactive powers into pu system. These base values are defined as follows:

(55)

The resulting pu expressions are independent of L_tot and f_s, as an example of instantaneous inductor current and power equations of (56), (57) and (58) for mode 1 shows below

(56)

(57)

(58)

-

The algorithm determines mode(s) that meet the required reference output power (P_ref(pu)).

-

Once the correct mode(s) is/are computed, the algorithm responds by calculating key metrics such active and reactive power values for each mode(s).

-

By using set of nested for loops, minimum reactive power search is performed, considering of all possible modes and results are listed.

-

From this list, the mode that generates minimum reactive power is selected.

-

Finally, the algorithm generates respective values of D₁, D₂ & D₃ for the optimum mode (D_1opt, D_2opt & D_3opt).

Figure 10. Flow chart of the TPS iterative optimization algorithm.

Figure 10. Flow chart of the TPS iterative optimization algorithm.

5. Results

In this section simulation and experimental verification are presented. To differentiate from the transformer voltage conversion ratio, an effective method is to perform analysis across the whole conversion ratio and power levels for each conversion ratio i.e,

(59)

Table 5. TPS Mode selection performance of the algorithm for R_V=2 at pref=0.25 pu and pref=0.5 pu.

Table 5. TPS Mode selection performance of the algorithm for R_V=2 at pref=0.25 pu and pref=0.5 pu.

Table 6. TPS Mode selection performance of the algorithm for R_V=4 at p_ref=0.25 pu and p_ref=0.5 pu.

Table 6. TPS Mode selection performance of the algorithm for R_V=4 at p_ref=0.25 pu and p_ref=0.5 pu.

Figure 11. Simulation results for Rv=2 (a) active power (b) reactive power, (c) CPS AC voltage waveforms for bridges A and B, (d) TPS AC voltage waveforms (e) Peak inductor currents, (f) RMS currents, (g) CPS control variable (h) optimum TPS control variables.

Figure 11. Simulation results for Rv=2 (a) active power (b) reactive power, (c) CPS AC voltage waveforms for bridges A and B, (d) TPS AC voltage waveforms (e) Peak inductor currents, (f) RMS currents, (g) CPS control variable (h) optimum TPS control variables.

Table 7. Converter Parameters.

Table 7. Converter Parameters.

Figure 12. (a) Block diagram of test system (b) Test set up.

Figure 12. (a) Block diagram of test system (b) Test set up.

- 

Low (LV) bridge and high voltage (HV) bridge single phase dual active converter bridges which are implemented using four active insulated gate bipolar transistor (IGBT) switches, with associated gate driver circuits for galvanic isolation between the switches common points and microcontroller common ground.

- 

Texas instruments F28335 Microcontroller.

- 

2 kHz nano-crystalline core transformer and external air core inductor.

- 

DC filters capacitors.

- 

DC power supplies powering sensor circuits, gate drivers, microcontroller, and cooling fans.

Figure 13. Measured voltage and current waveforms showing power reversal capability TPS algorithm.

Figure 13. Measured voltage and current waveforms showing power reversal capability TPS algorithm.

Figure 14. Experimental values of reactive power and efficiency for active power operations of (a) 0.5 pu (b) 0.25 pu when R_v=2.

Figure 14. Experimental values of reactive power and efficiency for active power operations of (a) 0.5 pu (b) 0.25 pu when R_v=2.

Figure 15. 0.5 pu measured AC and DC waveforms for optimum mode selection when R_v=2 (a) Modes 1,5 and 6 (b) Mode 1’ (c) Mode 2 (d) Mode 2’ (e) Modes 3 and 4.

Figure 15. 0.5 pu measured AC and DC waveforms for optimum mode selection when R_v=2 (a) Modes 1,5 and 6 (b) Mode 1’ (c) Mode 2 (d) Mode 2’ (e) Modes 3 and 4.

Figure 16. 0.25 pu reference power, AC and DC waveforms when R_v=2 (a) Mode 1 (b) Mode 1’ (c) Mode 2 (d) Mode 2’ (e) Modes 3 (f) Mode 4 (g) Mode 5 (h) Mode 6.

Figure 16. 0.25 pu reference power, AC and DC waveforms when R_v=2 (a) Mode 1 (b) Mode 1’ (c) Mode 2 (d) Mode 2’ (e) Modes 3 (f) Mode 4 (g) Mode 5 (h) Mode 6.

6. Conclusions

References

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