1. Introduction

2. System Architecture

3. Circuit Design

3.1. Pixel DC-Coupled Amplifiers

The schematic of the primary low-noise amplifier utilized in each recording channel is depicted in Figure 3. Following the topology proposed in [34], transistors M1 and M2 form the dc-coupled inverter-based amplifier of the system. In contrast to commonly used configurations employing differential amplifiers, the utilization of single-ended amplifiers offers notable benefits, such as reduced area occupancy and power dissipation, albeit at the cost of a decreased system rejection to interfering common-mode signals and power supply variations.

For the i-th channel, the output current produced by the main inverter-based amplifier is duplicated by means of the replicating transistors M8 and M9, which share the same source and gate nodes as the transistors comprising the inverter itself. The magnitude of the duplicated current is determined by the transconductance of M8 and M9. As such, by adjusting the aspect ratios of M8 and M9 to a fraction of the ratios of transistors M1 and M2, it is possible to replicate a scaled current with precision. This is done to ensure a more efficient occupation of on-chip area and a reduction in power consumption.

With reference to the schematic in Figure 3, transistors M3 and M4 provide a way to set the voltages of the floating rails of the input pixel amplifier. Acting as the terminal of the CMFB loop of the system, these transistors are diode-connected to avoid strong variations on the output high-impedance node, which would otherwise require Miller compensation. Additionally, the couples M3-M4 and M1-M2 must be sized equally in order to effectively reject the common-mode interference and also to prevent an increase in the IRN caused by the eventual mismatch.

Table 1. Transistor sizes for pixel amplifier and CMFB stage.

Table 1. Transistor sizes for pixel amplifier and CMFB stage.

MOSFET	Width	Length
M1-M3	$175\mu m$	$1\mu m$
M2-M4	$40\mu m$	$1\mu m$
M8-M11	$43.75\mu m$	$1\mu m$
M9-M12	$20\mu m$	$1\mu m$
M5	$12.70\mu m$	$15\mu m$
M6-M7	$5\mu m$	$10\mu m$
M10	$15\mu m$	$14.1\mu m$
M13-M14	$10\mu m$	$6.91\mu m$1

Biasing of the amplifier is achieved through the voltages $V_{bp}$ and $V_{bn}$ applied to the gates of transistors M5 and M6-M7 which, respectively, act as a current source and a current sink for the inverter. Concerning the couple M6-M7, in particular, connecting the gate nodes and the body nodes of the two transistors allowed to virtually obtain a transistor with a channel length capable of exceeding the upper limit set by the specific adopted technology [35]. Assuming an identical aspect ratio for both M6 and M7, the resulting composite transistor has an aspect ratio of

$$S=\frac{S_6·S_7}{S_6+S_7}=\frac{S_6^2}{2S_6}=\frac{S_6}{2}=\frac{W_6}{2L_6}.$$

(3)

4. Circuit Analysis

5. Simulation Results

5.1. Layout and Transistor Sizing

The layout of the inverter-based amplifier is reported in Figure 9, showing an area of $50\mu m\times 65\mu m$. Utilizing four metal layers, this layout encompasses all the transistors described in detail in Section 3.1. Notably, the smaller transistors (M8-M9 in Figure 3), responsible for replicating the scaled currents, are surrounded by the transistors of the inverter and the feedback transistors to mitigate potential mismatch between the devices.

With reference to Figure 3 and 4, table 1 summarizes the size parameters of the MOS transistors used both in the pixel amplifier and in the CMFB stage that makes up the closed loop. As stated before, the transistors that make up the inverter and the feedback transistors are sized equally by design. In order to accurately scale the currents of the main amplifiers, feedback transistors M8 and M9 are sized to have a width scaled by a factor 4. Transistors M5 and M6-M7 are sized with the intent of producing a bias current of 2.5 $\mu A$ for the main amplifying branch. Regarding the common-gate transistors implemented in the current-summing branch of the front-end, sizes have been chosen to be equal to the replicating transistors to minimize area occupation. For biasing purposes, the W and L parameters of transistors M10 and M13-M14 have been chosen to generate a current at least equal to the sum of the scaled, replicated currents.

Table 2 displays the sizing choices made with respect to the error amplifier. In this case, the parameters of the transistors have been set with the aim of obtaining a high open-loop gain for the amplifier, of at least 80 dB, with a phase margin 60°.

Table 2. Transistor sizes for error amplifier.

Table 2. Transistor sizes for error amplifier.

MOSFET	Width	Length
M15-M16	$5\mu m$	$8\mu m$
M17-M18	$1\mu m$	$20\mu m$
M19-M20	$10\mu m$	$1\mu m$
M21	$500nm$	$150\mu m$
M22-M23	$10\mu m$	$3\mu m$
M24	$180nm$	$10\mu m$
M25	$180nm$	$3\mu m$1

5.2. Circuit Simulations

The proposed front-end’s nominal behavior was simulated within the Cadence Virtuoso environment. To achieve results that closely resemble the actual implementation of the neural recording system, simulations were conducted by using the post-layout netlist with extracted parasitics. The circuit is biased with a dual voltage supply ($Vdd$=-$Vss$=0.5 V), while the total current used to bias a single channel is set at 3.5 $\mu A$.

Figure 10 shows that the inverter-based pixel amplifiers integrated in each recording channel boast a differential gain of 44.16 dB, alongside a high cut-off frequency exceeding 100 kHz. These metrics highlight the amplifiers’ ability to capture and amplify neural signals across the entire frequency spectrum that encompasses both local field potentials and action potentials as measured from the extracellular space.

As shown in Figure 11, further simulations have revealed a favorable SCMRR of 80.5 dB at low frequencies. Particularly noteworthy is the performance of the front-end within the range comprised between 0.1 Hz and 100 Hz, where the SCMRR maintains a value of at least 80 dB. A moderately high level of rejection is kept at higher frequencies, with the SCMRR exceeding 60 dB up to the frequency of 2 kHz.

The PSRR of the front-end, as indicated in Figure 12, shows a value of 72.55 dB at frequencies in the range that spans from 0.1 Hz to 100 Hz. For higher frequencies, the measured PSRR exhibits a similar behavior to the SCMRR, maintaining a level above 60 dB up until 2 kHz.

The input-referred noise spectrum of the input amplifier is presented in Figure 13, showing a noise level of 100 $nV/\sqrt{Hz}$ at 100 Hz and a value of 50 $nV/\sqrt{Hz}$ at 1 kHz. By integrating the noise spectrum across various frequency intervals, the noise performance of the amplifier was evaluated in terms of input referred noise (IRN). The achieved results are compiled in table 3.

Table 3. IRN values measured in different frequency intervals.

Table 3. IRN values measured in different frequency intervals.

	Bandwidth	Integrated Value
$IR{N}_{LFP}\left(\mu V_{rms}\right)$	$1Hz-300Hz$	$2.36$
$IR{N}_{AP}\left(\mu V_{rms}\right)$	$300Hz-7.5kHz$	$3.30$
$IR{N}_{TOT}\left(\mu V_{rms}\right)$	$1Hz-7.5kHz$	$4.04$

A widely used figure of merit that allows to relate the noise performance of the circuit with its power consumption and bandwidth is the noise efficiency factor (NEF) [37], expressed as follows:

$$NEF=IRN·\sqrt{\frac{2·I_{TOT}}{\pi ·V_T·4k_{b}T·BW}},$$

(33)

where $V_T$ is the thermal volta, $I_{TOT}$ is the total supply current of the amplifier, and $BW$ is the amplifier’s bandwidth (in Hz). By replacing in (33) the values of the total current required to bias the individual recording channel, the IRN and the bandwidth, we obtain

$$NEF=3.32.$$

In addition, the power efficiency factor (PEF) can be computed as

$$PEF=NE{F}^2·\left(Vdd-Vss\right).$$

(34)

5.3. Process and Mismatch Simulations

To assess the robustness of the front-end against PVT (Process, Voltage, and Temperature) and mismatch variations, the system underwent comprehensive testing via multiple simulations. Specifically, a Monte Carlo simulation comprising 200 iterations was conducted. The outcomes of these simulations are outlined in Table 4.

It must be noted that both the differential gain and the common-mode gain of the front-end demonstrate standard deviations within a 2 dB interval, consequently maintaining a similarly constrained SCMRR. Particularly, the differential gain exhibits minimal fluctuations around its mean value of 44.16 dB. Although the PSRR (Power Supply Rejection Ratio) variance is marginally higher, it remains moderately limited, with a mean of 74.11 dB and a variance of 6.30 dB. In both instances, the tested performance metrics yield favorable results, with both figure of merits exceeding 70 dB on average.

Table 4. Performance under mismatch variations.

Table 4. Performance under mismatch variations.

Parameter	Min	Max	Mean	Std. Dev.
$G_D\left(dB\right)$	$44.05$	$44.24$	$44.16$	$0.04$
$G_{CM}\left(dB\right)$	$-41.06$	$-34.00$	$-36.38$	$1.42$
$SCMRR\left(dB\right)$	$78.07$	$85.33$	$80.53$	$1.45$
$PSRR\left(dB\right)$	$64.89$	$94.52$	$74.11$	$6.27$
$V_{out\_DC}\left(mV\right)$	$-24.52$	$30.54$	$1.99$	$11.38$

Concerning the SCMRR and the PSRR, histograms related to the distribution of results over the 200 Monte Carlo iterations are presented in Figure 14 and 15.

To further test the robustness of the proposed front-end, a parametric simulation focusing on temperature variations was conducted. By gradually varying the operating temperature within the range [0 °C – 50 °C], the front-end’s gain and noise parameters, along with the rejection parameters, were evaluated accordingly (Tab. 5).

Regarding the differential gain of the input amplifiers, minimal fluctuations were observed; differently, the common-mode gain of the system exhibits a gradual decrease in value as the test temperature rises. Consequently, the SCMRR displays an increasing trend with growing temperatures, reaching a maximum value of 86.72 dB for 50 °C.

Conversely, the PSRR of the system tends to decrease in value with rising temperatures. In the range corresponding to the physiological conditions of the brain [38 °C – 41 °C], both PSRR and SCMRR are characterized by relatively minor variations, with values that manage to stay steady around 70 dB and 80 dB, respectively. When examining the noise performance of the front-end amidst temperature variations, it’s expected for the IRN of the system to experience a gradual rise. Nevertheless, with 4.23 $\mu V_{rms}$, considering the total bandwidth [1 Hz – 7.5 kHz], $IR{N}_{TOT}$ just barely exceeds its nominal value, measured at 27 °C.

Table 5. Performance under temperature variations.

Table 5. Performance under temperature variations.

Temp (°C)	0.00	10.50	21.00	31.60	42.10	50.00
$G_D\left(dB\right)$	$44.64$	$44.45$	$44.30$	$44.07$	$43.38$	$43.73$
$G_{CM}\left(dB\right)$	$-29.89$	$-32.20$	$-34.60$	$-37.33$	$-40.37$	$-43.99$
$SCMRR\left(dB\right)$	$74.53$	$76.65$	$78.90$	$81.40$	$84.25$	$86.72$
$PSRR\left(dB\right)$	$90.46$	$79.17$	$74.37$	$71.28$	$68.92$	$67.42$
$V_{out\_DC}\left(mV\right)$	$1.64$	$1.86$	$1.95$	$1.95$	$1.90$	$1.84$
$IR{N}_{LFP}\left(\mu V_{rms}\right)$	$2.27$	$2.30$	$2.34$	$2.38$	$2.41$	$2.44$
$IR{N}_{LFP}\left(\mu V_{rms}\right)$	$3.14$	$3.20$	$3.27$	$3.33$	$3.40$	$3.45$
$IR{N}_{LFP}\left(\mu V_{rms}\right)$	$3.87$	$3.95$	$4.02$	$4.10$	$4.17$	$4.23$

Continuing with the evaluation of the front-end, the following batch of simulations was conducted by varying the power supply voltage of ±10% of its nominal value. By consulting the results displayed in table 6, it emerges that variations in the differential gain were once again minimal. In a similar manner, the common-mode gain of the system varied between a minimum of -39.21 dB for (Vdd - Vss) = 1.1 V, and a maximum of -32.36, corresponding to (Vdd - Vss) = 0.9 V.

Integrating the input noise spectrum in the bandwidths of interest revealed a minor increasing trend in the band related to the local field potentials [1 Hz – 300 Hz] and a minor decreasing trend as it pertains to the band of the action potentials [300 Hz – 7.5 kHz]. Overall, the IRN measured in the total frequency band exhibits a negligible decrease.

Table 6. Performance under supply voltage variations.

Table 6. Performance under supply voltage variations.

Vdd-Vss (V)	0.90	0.94	0.97	1.02	1.07	1.10
$G_D\left(dB\right)$	$44.18$	$44.17$	$44.16$	$44.15$	$44.15$	$44.15$
$G_{CM}\left(dB\right)$	$-32.36$	$-33.93$	$-35.54$	$-37.03$	$-38.34$	$-39.21$
$SCMRR\left(dB\right)$	$76.54$	$78.10$	$79.70$	$81.18$	$82.49$	$83.36$
$PSRR\left(dB\right)$	$59.78$	$65.66$	$70.81$	$74.96$	$77.80$	$79.01$
$V_{out\_DC}\left(mV\right)$	$1.25$	$0.99$	$1.65$	$2.63$	$3.66$	$4.39$
$IR{N}_{LFP}\left(\mu V_{rms}\right)$	$2.32$	$2.34$	$2.36$	$2.37$	$2.39$	$2.41$
$IR{N}_{LFP}\left(\mu V_{rms}\right)$	$3.45$	$3.38$	$3.32$	$3.28$	$3.25$	$3.23$
$IR{N}_{LFP}\left(\mu V_{rms}\right)$	$4.16$	$4.11$	$4.07$	$4.05$	$4.03$	$4.03$

To conclude with the PVT analysis, the results of the simulations under corner variations are compiled in Table 7. Generally, it can be observed that the front-end’s robustness is quite favorable.

Table 8 shows a comparison between the front-end proposed in this work and various analog front-ends that were introduced in recent years. For most parameters, the simulation results presented in this section of the paper are comparable with modern state-of-the-art findings. Of particular importance is the area occupation per recording channel which, for our devised front-end, is reduced by a factor 3 with respect to the front-end introduced in [34], and is approximately equal to a tenth of the area occupied by the work presented in [33]. Additionally, thanks to the implemented closed CMFB loop, the CMI of the front-end hereby described is significantly higher than the ones measured for other devices.

Table 7. Performance under process variations.

Table 7. Performance under process variations.

Temp (°C)	TT	FF	SS	SF	FS
$G_D\left(dB\right)$	$44.16$	$43.59$	$44.73$	$44.09$	$44.17$
$G_{CM}\left(dB\right)$	$-36.04$	$-40.47$	$-32.38$	$-35.56$	$-24.97$
$SCMRR\left(dB\right)$	$80.20$	$84.06$	$77.11$	$79.65$	$69.14$
$PSRR\left(dB\right)$	$72.55$	$72.38$	$71.58$	$68.75$	$91.49$

Table 8. Performance comparison against state-of-the-art front-ends.

Table 8. Performance comparison against state-of-the-art front-ends.

	[33]	[38]	[39]	[34]	This Work
Year	2016	2018	2019	2022	$\mathbf{2024}$
Process	65 nm	180 nm	180 nm	180 nm	$\mathbf{180}$ nm
N° Channels	16	4	4	15	$\mathbf{15}$
Supply (V)	1	$1.8$	$\pm 1.2$	$\pm 0.5$	$\pm \mathbf{0}.\mathbf{5}$
P/Ch ($\mu W$)	$3.28$	$4.50$	$7.68$	$1.20$	$\mathbf{3}.\mathbf{77}$
A/Ch (${\mathrm{mm}}^2$)	$0.072$	$0.0214$	$0.012$	$0.004$	$\mathbf{0}.\mathbf{004}$
NEF/PEF	$3.19/10.2$	$1.94/6.77$	$2.65/8.43$	$2.65/7.02$	$\mathbf{3}.\mathbf{32}/\mathbf{11}.\mathbf{04}$
SCMRR (dB)	90	76	$>50$	75	$\mathbf{80}.\mathbf{50}$
PSRR (dB)	78	80	$>53$	74	$\mathbf{72}.\mathbf{55}$
CMI (${\mathrm{mV}}_{pp}$)	220	–	–	300	$\mathbf{400}$
IRN ($\mu$ ${\mathrm{V}}_{rms}$)	$4.13$	$3.20$	$3.87$	$5.30$	$\mathbf{4}.\mathbf{06}$
THD (%(@ ${\mathrm{mV}}_{pp}$))	$1\left(0.7\right)$	–	–	$1.6\left(2\right)$	$\mathbf{1}(\mathbf{1}.\mathbf{2})$

6. Conclusions

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