Preprint Review Version 1 Preserved in Portico This version is not peer-reviewed

A Comprehensive Review on Processing-in-Memory Architectures for Deep Neural Networks

Version 1 : Received: 20 June 2024 / Approved: 21 June 2024 / Online: 21 June 2024 (08:10:52 CEST)

A peer-reviewed article of this Preprint also exists.

Kaur, R.; Asad, A.; Mohammadi, F. A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks. Computers 2024, 13, 174. Kaur, R.; Asad, A.; Mohammadi, F. A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks. Computers 2024, 13, 174.

Abstract

This comprehensive review explores the advancements in processing-in-memory (PIM) techniques for deep learning applications. It addresses the challenges faced by monolithic chip architectures and highlights the benefits of chiplet-based designs in terms of scalability, modularity, and flexibility. The review emphasizes the importance of dataflow-awareness, communication optimization, and thermal considerations in designing PIM-enabled manycore architectures. It discusses different machine learning workloads and their tailored dataflow requirements. Additionally, the review presents a heterogeneous PIM system for energy-efficient neural network training and discusses thermally efficient dataflow-aware monolithic 3D (M3D) NoC architectures for accelerating CNN inferencing. The advantages of TEFLON (Thermally Efficient Dataflow-Aware 3D NoC) over performance-optimized SFC-based counterparts are highlighted. Overall, this review provides valuable insights into the development and evaluation of chiplet and PIM architectures, emphasizing improved performance, energy efficiency, and inference accuracy in deep learning applications.

Keywords

Deep Neural Network (DNN); Processing in Memory (PIM); Heterogeneous Architecture; Resistive ReRAM (ReRAM); Network On Chip (NoC); Latency; Power; Accuracy

Subject

Computer Science and Mathematics, Hardware and Architecture

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