3.2. Oil Backflow under Different Voltage Polarity
For addressing the phenomenon of oil backflow in EWDs, periodic reset signals were considered to be one of the most effective strategies to suppress oil backflow [
23]. A common reset method was to set the upper and lower electrodes to a same voltage, attempting to release the trapped charges in the dielectric layer by applying a zero voltage. However, experimental results revealed that there were significant differences in the speed of oil backflow under driving voltages of different amplitudes and polarities. The oil backflow curves for positive driving and negative driving at different voltage amplitudes were shown in
Figure 4. The graph illustrated the variations in luminance of the EWD panel before and after the application of voltage, as well as during the oil backflow process.
From oil backflow curves of positive driving in
Figure 4a, it was found that the luminance curve trends under different driving voltages were basically consistent when the luminance reached the maximum value. In addition, the luminance difference between adjacent voltages decreased as the amplitude of the driving voltage increased. The fundamental trend of oil backflow curves driven by negative voltage in
Figure 4b were consistent with that driven by positive voltage. However, the luminance variation between adjacent driving voltages increased with the increase of voltage amplitude. It was worth noting that a higher driving voltage amplitude was required for negative driving to match the luminance achieved with positive voltage driving. Comparing
Figure 4a and
Figure 4b, it could be seen that the oil backflow speed under negative driving was much higher than that under positive driving, especially when the luminance has just reached the maximum value. It was due to the fact that the charge trapping effect occurred continuously throughout the entire driving process, the dielectric layer under negative driving exhibited enhanced charge trapping capability and speed. This characteristic indicated that a short-term negative driving pulse may be more effective in suppressing oil backflow phenomenon.
The direct consequence of the oil backflow phenomenon was a continuous decrease in luminance of the EWD panel. Therefore, the average rate of luminance decrease over a period of time was used as an indicator to the speed of oil backflow. For the positive driving, a time range from 200 milliseconds to 500 milliseconds was selected. For the negative driving, the selected time period started at 198 milliseconds and ended at 208 milliseconds. During initial power on of the device, the movement of oil and the charge trapping occurred simultaneously. Thus, the process of charge trapping could not be fully represented by the variation of luminance at that time. The spreading process was closely related to charge trapping only after the oil has shrunk to the maximum extent. Therefore, the luminance variations within these two designated time periods were selected to characterize the rate of oil backflow.
To observe the difference, we have plotted the relationship curves of oil backflow speed versus driving voltage amplitude under positive and negative driving conditions, as illustrated in
Figure 5. It could be seen that there was a significant difference in the oil backflow speed of EWD under two polarity driving voltages. The luminance difference indicated that the oil backflow speed exhibited a voltage polarity dependence. Compared with negative driving, the oil backflow speed under positive driving was lower and had a smaller fluctuation range. The trend of oil backflow speed was indicated by the red dashed line in the figure. In the positive driving, the oil backflow speed under different driving voltages could be approximated as a constant value. Unlike the positive driving, the oil backflow rate decreased with increasing of voltage amplitude in the negative driving. This phenomenon indicated that charges were more easily trapped by the dielectric layer when the negative voltage was applied.
By systematically studying the influence mechanism of driving voltage polarity on charge trapping speed, an important basis could be provided for optimizing the driving mode and material selection of EWDs. When designing a driving circuit, it was necessary to fully consider the different trapped charge amounts of positive and negative polarity voltages. The negative impact of charge trapping on device performance could be mitigated by choosing a reasonable driving waveform.
3.3. Design of Driving Waveform
Previous studies have shown that flipping the voltage polarity was an effective method to eliminate the charges trapped by the dielectric layer in electrowetting-on-dielectric (EWOD) devices [
34]. During the driving process of EWDs, the driving waveform with unchanged voltage polarity was called the unipolar driving waveform. The driving waveform composed of positive and negative voltages was called the bipolar driving waveform. In the case of AM-EWDs, inserting a reset driving waveform between driving frames would occupy the frame time. The conventional unipolar reset driving waveform was shown in
Figure 6 (S
5) [
30]. It was typically comprised of a combination of several high and low levels. The low-level voltage was used to release the trapped charge in the dielectric layer. The high-level voltage was used to accelerate the activation of pixels, allowing the EWD to return to its original luminance prior to the application of the reset waveform. The insertion period of reset signal, the closing time
, the opening time
, and the maximum driving voltage
in the reset driving waveform must be set in accordance with the oil backflow parameters in the EWD.
In the AM-EWDs, the TFT structure shown in
Figure 1d is the key component for driving the pixels. The potential between pixel electrodes was indirectly regulated by the voltage on each pin of TFT. As shown in
Figure 6, the pixel voltage change caused by the voltage polarity flipping of the common electrode was analyzed when pixels were kept open. The initial state and three complete scanning frames were contained in the figure. Phase (a) represented the initial state when the electrode voltage between pixels was zero. Each scanning frame was comprised of two distinct phases. In the first scanning frame, the output voltage of the source electrode in phase (b) was -15 V. When the output of the Gate electrode was high level, the actual voltage between the pixel electrodes was 30 V. When the polarity of common electrode voltage
was flipped from positive to negative in phase (c), TFT was in the state of open-circuit due to the extremely high electrical impedance (about
). In an ideal state, the voltage between pixel electrodes was remained at a constant level. One of electrodes in the pixel had a potential of -45 V, as illustrated by the red line segment. However, the source and the gate of the TFT would conduct to form a discharge circuit when the voltage difference
between the gate and the source was less than the threshold voltage
. The potential at one end of the pixel was reduced to -20V by the limitation of gate voltage, as illustrated by the blue line segment. At this time, the actual driving voltage across the pixel was about 5 V. In the second scanning frame, the output of the gate electrode in phase (d) was a high level, and the actual driving voltage across the pixel was 30 V. When the voltage polarity of the common electrode was flipped during phase (e),
was still greater than
. Therefore, the TFT was remained at the state of open-circuit, and the actual driving voltage across the pixel was remained at 30 V. Subsequently, the third and fourth frames would repeat the voltage changes of the first and second frames, respectively. With two scanning frames as a cycle period, the average driving voltage across pixels was 17.5 V. During this driving process, the voltage polarity between pixel electrodes did not change as the polarity of
flipped. Accordingly, this methodology was only capable of generating the unipolar reset driving waveform illustrated in
Figure 6 (S
5).
In the experimental setup, the storage capacitor architecture of the AM-EWD was a Cs on common structure. Therefore, the influence of feed through voltage on pixel voltage cannot be ignored during the driving process. On the TFT substrate used in the experiment, the UC8430 chip was employed as the gate driver. The output of the gate driver was limited to high and low levels, which belong to two-level driving. In the principle of two-level driving system, the generation of feed through voltage was mainly due to changes in other voltages on the panel. The accuracy of the pixel electrode voltage was impacted by the feed through voltage, which was transmitted through parasitic capacitance, storage capacitance, and pixel capacitance. When the common electrode voltage was remained at a constant value, the most significant impact on the driving voltage of pixel was exerted by the feed through voltage generated from changes of the gate driver voltage. At this point, the feed through voltage could be derived based on the conservation of electric charge law, as shown in Equation (1).
Where,
and
represented voltages when the gate line was open and closed, respectively.
,
, and
represented the parasitic capacitance, pixel capacitance, and storage capacitance, respectively. Apart from the change of gate driver voltage, the driving voltage of the pixel was also influenced by the movement of oil under different voltages. The EWD panel used in experiments required a 30 V driving voltage to meet the driving demands. Given that the maximum output of source driver was ±15 V, the common electrode voltage could only be set to either 15 V or -15 V. To eliminate the impact of feed through voltage on the driving voltage of pixel electrode, the voltage of the common electrode required to be adjusted. The primary electrical parameters of the TFT substrate used in the experiment were shown in
Table 2. It was found that the pixel capacitance increased from 0.14 pF to 0.45 pF when the driving voltage of the pixel was increased from 0 V to 30 V. At a pixel capacitance of 0.15 pF, the pixel charging rate was 96%. When the pixel capacitance increased to 0.45 pF, the charging rate dropped to 94%. Therefore, the dynamic range of the pixel charging rate was between 94% and 96%. Calculations indicated that the feed through voltage varied between 1.3 V and 1.6 V at this time. Consequently, the compensation voltage for the common electrode in practice was required to be adjusted according to the pixel capacitance or the pixel driving voltage. To eliminate the impact of the maximum feed through voltage, the compensation voltage for the common electrode was set to the maximum feed through voltage.
The dielectric layer of the display device used in the experiment was a non-polar polymer Teflon with high electrical resistivity. There were some defects and impurities in Teflon materials which could trap electrons or holes. When a voltage was applied to pixel electrodes, a local electric field was also generated on the surface of Teflon film. The movement of free electrons or holes could be accelerated by the local electric field. This dynamic process increased the possibility of their interaction with defects or impurity structures in the material. As a result, the local electric field indirectly increased the probability of charge carriers (including free electrons and holes) being trapped by internal defects or impurities. Typically, a periodic reset driving waveform was employed to reduce the charge trapping by the dielectric layer. It was equivalent to release the trapped charges by short-circuiting the upper and lower substrates. Charge trapping had an impact on the actual pixel driving voltage, which was reflected in the luminance variation through oil movement. Hence, the relationship between charge trapping and driving voltage could be investigated through luminance variations of EWDs. It was assumed that the relationship among luminance
, driving time
, and driving voltage
was depicted in Equation (2).
Where,
was the charge trapping characteristic parameter, representing the influencing factors of the EWD pixel structure and material.
denoted the minimum luminance generated by oil’s light transmittance without a voltage applied on the EWD.
indicated the starting time of oil backflow. It was assumed that the luminance during oil backflow had a linear relationship with the driving voltage, as depicted in Equation (3).
Where, β was a constant coefficient.
represented the luminance variation, and
represented the number of trapped charges. By combining with Equation (2) and Equation (3), the functional relationships among the applied positive, negative polarity voltage amplitudes and the luminance variation were shown in Equation (4) and Equation (5).
Where,
and
represented driving voltages under positive and negative driving conditions, respectively.
and
were the charge trapping characteristic parameters under
and
.
and
were durations of
and
, respectively. Since the number of trapped charges during the driving process should be maintained at zero, the relationship between the luminance variation during the positive and negative polarity driving processes was shown in Equation (6).
By combining Equation (4), Equation (5), and Equation (6), the relationship between the positive and negative driving voltages could be described by Equation (7).
Based on the above analysis, it was evident that the amplitude of the positive and negative polarity voltages could be determined by the driving time
and the charge trapping characteristic parameter
. The value of
could be approximately represented by the slope of the oil backflow curve. Assuming that the positive polarity driving voltage was 30 V, the corresponding driving duration was
. Similarly, for a negative polarity driving voltage of -10 V, the corresponding driving duration was
. If
was taken as the starting time, then the relationship between the driving times
and
could be described by Equation (8).
According to the experimental results,
was found to be -0.0119 and
to be -0.7680. It could be obtained that
was equal to 21.5126
according to Equation (7). The driving time for the positive voltage of 30 V was 21.5126 milliseconds. The driving time for the reset voltage of -10V was 1 millisecond. In AM driving, the duration of luminance fluctuation caused by the reset signal should be less than the duration of one frame. Building upon this insight, a driving approach with the frame-interleaved reset waveform was developed to minimize luminance fluctuation within frame duration. To meet the driving timing requirements of AM-EWD, the inter-frame reset waveform could only be applied during the vertical front porch (VFP) and horizontal back porch (HBP) periods. The pixel charge and discharge time on the TFT substrate was set as 33 microseconds. So, the refresh time for the active area of AM-EWD was 480 gate lines multiplied by 33 microseconds per line, totaling 15.84 milliseconds. At a refresh rate of 60 Hz, the available time for VFP and HBP was reduced to 830 microseconds. Consequently, the duration of reset driving waveform must be appropriately adjusted within 830 microseconds to meet the refresh time requirement of the active area. The schematic of the inter-frame bipolar reset waveform for the AM-EWD was illustrated in
Figure 7. By adjusting the amplitude of the gate voltage
during the reset period, the negative polarity voltage applied to the pixels could be regulated.