Once the M-point signal, consisting of J periods, is stored in memory, it can be synthesized directly without requiring phase-locked loops. Different frequencies of the waveform can then be produced by changing the rate the phase values are processed, and using techniques like scale, add, and multiply, various waveforms can be generated. The stored waveform in memory is added to the pre-distortion calibrated codes in the digital domain and the result is sent to as digital input codes to the DAC to obtain desired waveform at high purity. The pre-distortion codes are obtained using an algorithm which uses the results from the simultaneous testing of the DAC and ADC (details will be provided later). It is imperative that for every sample, the value is held by the zero-order hold circuit at the output of the DAC. The next sub-sections provide detailed description of the proposed generator.
3.1. R-2R DAC with Redundancy
At the heart of the waveform generator in
Figure 1 is the low-cost N-bit DAC. Since the DAC is the main stimulus source to generate the signal, its performance is critical. However, the matching requirement required to achieve good performance is the major contributor to the cost required to implement a DAC. To achieve good matching, careful layout strategies are adopted to cancel gradient errors, but to reduce the local random mismatches, the caveat is to push more area into the DAC, which increases the cost. The normalized standard deviation of resistor,
R can be estimated as
Where
is the pelgrom parameter and
A is the area of the resistor [
23,
24]. It is evident from (
1) that a reduction in resistor mismatch requires an exponential increase in the area. Conventionally, the R-2R DAC has binary weighted bits, in the ideal case [
25,
26]. However, mismatches and other errors result in the deviation from the ideal weights. In our approach, we relax the matching requirement by introducing redundancy, making the DAC sub-radix, and leading to drastic reduction in cost. An extra bit, the redundant bit, is added to introduce redundancy and through a simple on-chip calibration technique, we achieve very good linearity performance.
Figure 2 shows the proposed R2R DAC with redundancy. The DAC is segmented into MSB and LSB by the redundant bit,
, which is formed by the T-network of resistors
,
and
.These resistors are sized so that the weight of
can cover the worst-case mismatch of the MSB bit. Since the MSB bit of the R-2R ladder has the largest weight,
’s weight will be able to cover lower MSB bits’ weight as well.
Although, the main constraint for sizing is to obtain a weight high enough to cover the worst-case mismatch of the MSB segment, another constraint is to ensure that the first MSB bit has a lower weight than the sum of the LSB bits weight. With the redundant bit, the LSB bits are still binary weighted and the MSB bits are sub-radix. This helps introduce calibratable negative jumps in the transfer characteristic of the DAC, which helps avoid the possibility of large uncalibratable positive jumps.
3.3. ADC DAC Simultaneous Test Scheme
The setup used to implement the testing scheme is shown in
Figure 3. The resolution of the DAC is
with an extra bit,
for redundancy and the resolution of the ADC is
. For a user input code to the DAC,
, there is a corresponding DAC output voltage,
(
). Similarly, for an ADC transition voltage,
, there is also a corresponding transition output code from
to
. It is worth noting that the ADC will have
such transition voltages and the DAC will have
output voltages.
For an input code
to the DAC, the corresponding output voltage
can be expressed as
where
is the DAC INL at code
.
The output voltage of the DAC is sampled by the ADC, which correspondingly produces a code,
. The expression for the sampled voltage
at code
is shown in Equation (
3).
where
is the ADC quantization error at code
i.
A detailed expression for
at code 1 is shown in Equation (
4).
Combining Equations (
3) and (
4) yields Equation (
5) shown below.
where
is the ADC INL at code 1.
From
Figure 3, the output voltage of the DAC is fed to the ADC input. Using this relationship, we can combine Equations (
2) and (
5) to obtain a simplified Equation (
6) for a DAC input code 2 (
).
Equation (
6) shows the ADC and DAC INL relationship for the case where the redundant bit in the DAC is set to low. A similar equation, shown in Equation (
7), can be obtained when the redundant bit
is set to high.
where
is the weight of the redundant bit,
.
Using Equations (
6) and (
7), we can estimate the INL of both the DAC and ADC. It is worth noting that solving these equations for high-resolution data converters can be very computationally intensive because of the large dataset. To alleviate this issue, we used the segmented model described in [
27]. In segmented architectures, there is no correlation between the INLs at different codes. For an
-bit DAC, assuming we have a segmentation
,
, and
representing the "most significant bits," "intermediate significant bits," and "least significant bits" respectively, for each of the MSB, ISB, and LSB segments, there are
,
, and
errors associated with them. If these errors associated with the MSB, ISB, and LSB of the DAC are represented by
,
, and
respectively, then the INL at DAC code
is
where
,
, and
are the codes associated with the MSB, ISB, and LSB segments for a DAC code
.
Similarly, for a code
associated with the ADC, if the corresponding errors associated with the MSB, ISB, and LSB are denoted by
,
, and
respectively, then the INL at ADC code
is shown in Equation (
8).
Using the segmented models helps reduce the size of the dataset. The number of parameters we have to estimate will reduce from to , where . A similar reduction is also seen for the ADC.
It is worth noting that the redundant bit segments the DAC into an MSB and LSB DAC, and the segmented model is used to segment the errors associated with the full DAC transfer characteristic. It must also be emphasized that if the INL is computed based on the end-point fit line definition, then .
Equations (
8) and (
9) suggest that, once the errors associated with the DAC and ADC are accurately estimated, the INL associated with them can also be estimated accurately. Combining Equations (
6)–(
9) in matrix notation, we obtain Equation (
10) below
Where
A is a matrix of size shown in Equation (
11)
The additional 1 in (
11) represents the relative offset,
, between the DAC and ADC. Compared to the scheme in [
27], we need not estimate the shift voltage to the DAC as it is already known as the weight of the redundant bit,
.
b is a column vector formed by the equations on the right-hand side of Equations (
6) and (
7).
Since the size of
M is far greater than the expression in (
12), we can use least squares to estimate the unknown vector
e, which contains
,
,
,
,
,
, and
.
The estimate of
e is shown in Equation (
13).
With the estimate
, we can construct the DAC and ADC full code non-linearity with Equations (
8) and (
9) respectively.
3.4. DAC Calibration via Pre-Distortion
Calibration aims to minimize the error associated with the DAC to ensure that a high-purity signal is obtained. In general, we want to minimize the difference between the calculated output levels of the DAC and the desired analog value. Ideally, the search method where all the output levels of the DAC are stored, and then when a particular voltage is desired, a search algorithm will look to find the desired voltage level and send this code to the DAC. This method achieves the best minimization; however, it causes a large hardware overhead, such as the area for storing all output voltages in memory. Also, the design effort required to implement this is high.
We propose a simple method where the estimated DAC INL,
, is added to the user input code and is rounded to obtain the pre-distortion codes to the DAC. For a user input code,
, Equation (
14) shows the corresponding pre-distortion code,
.
By adding the INL to the initially desired user input code, we can move the code very close to the optimal code which would be found using the search calibration method. The pre-distortion algorithm would be much closer to the search method if only the INL is the same across this small range, this is however not always true. This method shows very good performance but not as good as the search method. Although there will be slightly more distortion and noise with the pre-distortion method, it is not more cost effective and does not require large memory. Another benefit of method is that, if the number of data points for the FFT data is less than the number of codes of the DAC, then we only need to calculate INLs for the number of data points relaxing the complexity and resulting in extra cost savings. It is worth noting that, in our scheme these user input codes come from the desired digital waveform. This implies that we can generate not only sine waves but other wave-forms at high purity.