Version 1
: Received: 29 September 2024 / Approved: 30 September 2024 / Online: 30 September 2024 (10:36:34 CEST)
How to cite:
Trape, M. A.; Hellany, A.; Rizk, J.; Nagrial, M. Design and Performance Analysis of a Platform-Based Multi-phase Interleaved Synchronous Buck Converter Using Si MOSFET. Preprints2024, 2024092391. https://doi.org/10.20944/preprints202409.2391.v1
Trape, M. A.; Hellany, A.; Rizk, J.; Nagrial, M. Design and Performance Analysis of a Platform-Based Multi-phase Interleaved Synchronous Buck Converter Using Si MOSFET. Preprints 2024, 2024092391. https://doi.org/10.20944/preprints202409.2391.v1
Trape, M. A.; Hellany, A.; Rizk, J.; Nagrial, M. Design and Performance Analysis of a Platform-Based Multi-phase Interleaved Synchronous Buck Converter Using Si MOSFET. Preprints2024, 2024092391. https://doi.org/10.20944/preprints202409.2391.v1
APA Style
Trape, M. A., Hellany, A., Rizk, J., & Nagrial, M. (2024). Design and Performance Analysis of a Platform-Based Multi-phase Interleaved Synchronous Buck Converter Using Si MOSFET. Preprints. https://doi.org/10.20944/preprints202409.2391.v1
Chicago/Turabian Style
Trape, M. A., Jamal Rizk and Mahmood Nagrial. 2024 "Design and Performance Analysis of a Platform-Based Multi-phase Interleaved Synchronous Buck Converter Using Si MOSFET" Preprints. https://doi.org/10.20944/preprints202409.2391.v1
Abstract
This paper proposes a design for a platform-based Multi-phase Interleaved Synchronous Buck Converter (MISBC) using Silicon (Si) based Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). A custom platform was developed to compare the theoretical performance of a MISBC circuit simulated with Multisim and compared it with a prototype that was built at Western Sydney University. The work disclosed in this manuscript describes some steps adopted during the selection of each component and technical considerations taken during the design of the Printed Circuit Board (PCB). The platform designed has a maximum power output of 260 Watts, with a buck reduction of the nominal voltage from 97 Volts to 24 Volts at a maximum switching frequency of 50 kHz. This switching frequency is achieved with an open-loop circuit configuration coupled with synchronized signal generators, used to validate the dead band required between the activation of each MOSFET implemented in a half bridge configuration. A summary of the results based on the duty cycle required to achieve the buck voltage desired highlights the advantages of each operating mode of the MISBC circuit, where the theoretical performance is compared against the data acquired during functional evaluations of the prototype, allowing further interpretations towards the optimal control algorithm required to maximize the performance output of MISBC circuits.
Keywords
DC-DC Converter; Buck Converter; Si MOSFET; Power Electronics; Circuit Design
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
