An ultra-low power (ULP), power gated static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates in sub-threshold voltage ranges from 300mV to 500mV. The proposed SRAM has tendency to operate in low supply voltages with high static and dynamic noise margins. The IoT application involves battery enabled low leakage memory architecture in subthreshold regime which has low power consumption. Therefore, to improve power consumption along with better cell stability, a power gated 10T SRAM is presented. The proposed cell uses a power gated p-MOS transistor to reduce the leakage power or static power in standby mode. Moreover, due to the schmitt triggering and read decoupling of 10T SRAM the static and dynamic behavior in read, write and standby mode has shown enhanced tolerance at different process, voltage and temperature (PVT) conditions. The proposed SRAM shows better results in terms of leakage power, read static noise margin (RSNM), write static noise margin (WSNM), write-ability or write trip point (WTP), read-write energy and dynamic read margin (DRM). Further, these parameters are observed at 8-Kilo bit (Kb) and compared with already existing SRAM architectures. It is observed that the leakage power is reduced by 1/81×, 1/75× of the conventional 6T (C6T) SRAM and read decoupled 8T (RD8T) SRAM, respectively at 300mV VDD. On the contrary, RSNM, WSNM, WTP and DRM values are improved by 3×, 2×, 11.11% and 31.8% as compared to C6T SRAM, respectively. Similarly, proposed 10T has 1.48×, 25% and 9.75% better RSNM, WSNM and WTP values as compared to RD8T SRAM, respectively at 300mV VDD.

Nanoscale structuring/printing is of interest for range of applications in 3D subtractive and additive manufacturing (3D^+/-). Basic principles of light field enhancement and control at the nanoscale are overviewed in this section/chapter for bulk, surface, and localised plasmons (1D, 2D, and 3D localisation, respectively). All these plasmons are resonant phenomena which have common Lorentzian spectral lineshape which relates refractive and absorption properties as well as defining the phase of transmitted and scattered light. Localisation of light at the nanoscale creates the possibility of modification with matching resolution. Harnessing this light enhancement can be demonstrated as a "nano-pen" for direct write nanolithography.

Conventional deduplication systems face critical challenges such as excessive write amplification, high read/write latency, and sub-optimal storage utilization. These limitations often undermine the performance benefits of deduplication by slowing down I/O acknowledgements, due to amplified deduplication I/Os, excessive data chunk replication and strict consistency requirements. To address these issues, we present Speed-Dedup, a novel deduplication framework that employs a deduplicated primary - semi deduplicated replica object approach. This strategy reduces write amplification by restricting deduplication to the primary object while maintaining a semi-deduplicated replica object used for immediate read/write acknowledgements, thus enhancing I/O latency and storage efficiency. Speed-Dedup also replaces traditional strong consistency models with eventual consistency, allowing for non-blocking read operations and improving overall system throughput. Experimental results demonstrate that Speed-Dedup significantly outperforms traditional methods like GRATE and CAO, showing up to 21% improvement in I/O performance under low deduplication ratios and maintaining 14% or more gains under higher ratios. Additionally, write amplification is substantially reduced, and latency improves by over 100%, with faster recovery times during system failures. These findings highlight the effectiveness of Speed-Dedup as a scalable and efficient solution.

Electronic designers nowadays are facing two challenging demands for various applications: miniaturization and increased functionality. To satisfy these seemingly opposed requirements, reducing the number of mounted components—and thus solder joints—in PCB designs becomes an attractive approach by directly printing passive components such as embedded resistors into the circuit. This approach can also potentially increase the reliability, such as “mean time between failures” (MTBF), while reducing the circuit board size. With its unique capabilities for non-contact precision material deposition, the Aerosol Jet® direct-write technology has been enabling additive manufacturing of fine-feature electronics conformally onto flexible substrates of complicated shapes. The CAD/CAM controlled relative motions between substrate and print head allows convenient adjustment of the pattern and pile height of deposited material at a given ink volumetric deposition rate. To date in the printed electronics industry, additively printing embedded polymer-thick-film (PTF) resistors has mostly been done with screen printing using carbon-based paste inks. Here we demonstrate results of Aerosol Jet® printed PTF resistors of resistance values ranging from ~50 W to > 1 kW, adjustable (among several variable parameters) by the number of stacked layers (or print passes with each pass depositing a fixed amount of ink) between contact pads of around 1 mm apart with footprint line typically < 0.3 mm. In principle, any ink material that can be atomized into fine droplets of 1 to 5 microns can be printed with the Aerosol Jet® system. However, the print quality such as line edge cleanliness can significantly influenced by ink rheology which involves solvent volatility, solids loading, and so on. Our atomizable carbon ink was made by simply diluting a screen printing paste with a compatible solvent of reasonable volatility, which can be cured at temperatures below 200 ^oC. We show that Aerosol Jet® printed overlapping lines can be stacked to large pile height (to reduce the resistance value) without significant increase of line width, which enables fabricating embedded resistors with adjustable resistance values in a limited footprint space.

Energy-efficient microprocessors are essential for a wide range of applications. While near-threshold computing is a promising technique to improve energy efficiency, optimal supply demands from logic core and on-chip memory are conflicting. In this paper, we perform static reliability analysis of 6T SRAM and discover the variance among different sizing configuration and asymmetric minimum voltage requirements between read and write operations. We leverage this asymmetric property in near-threshold processors equipped with voltage boosting capability by proposing an opportunistic dual-supply switching scheme with a write aggregation buffer. Our results show that proposed technique improves energy efficiency by more than 21.45% with approximate 10.19% performance speed-up.

At present, diversified and highly concurrent businesses in the Internet industry often require heterogeneous databases formed by multiple databases to meet the needs. This report introduces database kernel SG-ColBase we developed. After achieving read and write concurrency control, data rollback, atomic log writing, and downtime data redo to ensure complete transaction support. The parallelism of database kernel execution is extended through field level locks and snapshot reads. Use the Bloom filter, resource cache pool, memory pool, skip list, non blocking log cache, and asynchronous data writing mechanism to improve the overall execution efficiency of the system. In terms of data storage, column storage, logical key and LSM-tree are introduced. While improving the data compression ratio and reducing data gaps, all disk data operations are written in incremental order. With the characteristics of asynchronous batch operation, the data writing speed is greatly improved. Thanks to the continuous feature of vertical data brought by column storage, the disk scanning brought by vertical traversal is reduced, which is a qualitative leap in efficiency compared with traditional relational databases in the big data analysis scenario. SG-ColBase can reduce the use of heterogeneous databases in business and improve R&D efficiency.