We form the neuromorphic dendritic neuron model (
Figure 1c,d) based on the physics of the neurotransistor [
48] (
Figure 1e), so we call it ‘dendristor.’ We selected the existing neuromorphic hardware platform that can stably and closely mimic dendritic properties, and therefore, is able to show various spatiotemporal performances of the dendritic computation. The Si-based transistor provides stable current dynamics and good controllability as a device compared to other types of electronic devices. The connection of the multiple specular transistors (
Figure 1c) provides a summated source-drain current like the dendritic signal summation at the point where the dendritic branches are combined. The dendristor model is formed based on the physical phenomena of metal-oxide-semiconductor field-effect transistors (MOSFETs) covered with ion-doped soft dielectric material, which includes mobile ions to mimic the neuronal membrane’s ion diffusion in the neuronal membrane [
48]. The synaptic inputs are applied as gate voltage (
vGS,ij, where i is the number of dendritic branches and j is the number of the synaptic inputs) to metal electrodes, G
ij (
Figure 1c) on the dendritic branch and transforms to output current,
IDS. The physical design and properties of the device model are explained in Supplementary Information S1.
Figure 1d illustrates the simplified LT-SPICE circuit model, which illustrates a single dendristor branch formed with the large-signal MOSFET model and the sub-circuit of the ion-doped sol-gel dielectric film. The circuit model has three functional parts: (i) a circuit for the adaptive polarization of ions occurring in the film triggered by each gate, (ii) a combined RC circuit of the dendritic integration film contacting Si nanowire oxide that provides effective gate voltage to the transistor channel, and (iii) the MOSFET large-signal circuit (
Figure 1d). The mathematical model and corresponding phenomena on a neurotransistor [
48] are explained in Supplementary Information S2. The description of the circuit elements and their parameters are summarized in Methods. The current output dynamics of the neurotransistor and the dendristor model with single gate input in
Figure 1e demonstrates how closely the model simulates the device physics. Most important element in the dendritic computation is the variable resistance,
Rhj, which identifies each synaptic input’s location related to the length between the synaptic input and the dendritic integration center (
i.e., the channel of the transistor).
Rhj is updated by the present gate input (
vGS,j) and the internal state of the film, which can be defined as an effective gate voltage (
vgS, the voltage between node g and node S) of the transistor, and their relation is described in the following equation:
where
rhj is a constant resistance parameter (unit: Ω) of the film between the
jth gate input and the conductive channel output, and
VA,j is a voltage amplitude of
vGS,j. As the resistance is relevant to the length of the ionic migration path,
rhj is the distance-correlated factor based on the film distance from the nanowire channel to the gate. Hence, each synaptic input signal is differently weighted by
rhj in a single dendritic branch to map the spatial information. The effective gate voltage,
vgS, is another critical value since it defines
Rhj and
IDS (
Figure 1d). The built-in potential in the film (
vgS) evolves nonlinearly with respect to
vGS,j. In sum, the dendritic integration of multiple inputs in a dendritic branch is obtained as a combined process of the time-varying nonlinear
vgS change and the nonlinear
vgS-to-
IDS transfer function of a MOSFET. All results below are obtained from the LT-SPICE circuit simulation
.