Comparative Study of IGBT and SiC MOSFET Three-Phase Inverter: Impact of Parasitic Capacitance on the Output Voltage Distortion

Preprint

Article

Comparative Study of IGBT and SiC MOSFET Three-Phase Inverter: Impact of Parasitic Capacitance on the Output Voltage Distortion

Altmetrics

Downloads

171

Views

Comments

A peer-reviewed article of this preprint also exists.

This version is not peer-reviewed

Submitted:

15 August 2023

Posted:

17 August 2023

You are already at the latest version

Alerts

Abstract

This study investigates the nonlinearities in three-phase inverters for SiC-based systems and compares their performance to IGBT-based systems. An analytical model of inverter voltage distortion is developed, which accounts not only for dead time (td), switching delay time, switching frequency (fs), and voltage drops of power devices, but also for output parasitic capacitance (Cout). Experimental tests validate the model, which provides a more accurate estimate of the inverter’s output phase voltage distortion. The power device characteristics are obtained from datasheets, while Cout is determined through experimentation. Three-phase inverters with varying switching frequencies, fundamental frequencies, and dead-time values are used in simulations and experiments to determine the influence of nonlinearity on phase voltage deviation and current distortion. The results show that, due to SiC devices’ faster switching time, the phase voltage deviation and phase current distortion are lower in SiC-based inverters than in IGBT-based ones for high-frequency applications, as the dead time can be reduced.

Keywords:

Subject: Engineering - Electrical and Electronic Engineering

1. Introduction

High-speed electric motor drive systems have gained significant popularity in various industries due to their compact size, lightweight design, and impressive power density. These systems operate at exceptionally high fundamental frequencies (

f_{0}

), typically in the kilohertz range, necessitating inverters capable of handling such demanding switching frequencies.

However, traditional silicon (Si) IGBT technology has limitations in achieving high switching frequencies, resulting in compromised current quality at higher fundamental frequencies. The decrease in the frequency modulation index (

f_{s} / f_{0}

) with increasing fundamental frequency leads to higher total current harmonic distortion (THD) [1]. Additionally, Si-IGBT technology exhibits drawbacks in terms of efficiency, operating temperature, and power density.

To overcome these limitations, SiC MOSFET technology has emerged as a superior alternative to Si-IGBT technology. SiC MOSFETs offer advantages such as higher efficiency [2,3,4], increased switching frequency, extended operating temperature capabilities [5,6], and improved power density [7]. These properties make SiC MOSFETs a preferred choice for high-speed electric motor drive systems, surpassing the limitations of Si-IGBT technology.

In this context, SiC-based inverters have been identified as suitable for high-speed machines requiring high fundamental and switching frequencies to minimize total harmonic distortion of the current [8]. The voltage deviation and current distortion in the inverter are directly proportional to the increasing

f_{s}

This research aims to model, study, and compare the influence of various parameters, including dead-time, switching delay time, voltage drop, and parasitic capacitor output, on voltage and current distortion in SiC-based and IGBT-based inverters for high-speed machines. The fundamental frequencies tested range up to 3400 Hz, while the switching frequencies vary from 10 kHz to 100 kHz.

The remainder of this paper is organized as follows. Section 2 presents the proposed analytical model. Section 3 explores the influence of imperfections in the considered components in detail. Section 4 presents the experimental results. Finally, the conclusion is provided in the last section.

2. Analytical Modeling of a three-phase voltage source inverter and Imperfections

2.1. Three-phase voltage source inverter modeling

Figure 1 illustrates a three-phase voltage source inverter (3Ph-VSI) used for general applications. In this figure, the load current is positive when it flows from the source to the load, and negative when it reverses its direction.

The modeling of the 3Ph-VSI is initially developed without considering imperfections such as dead times, delays in component startup and shutdown, voltage drops, and parasitic capacitances. Therefore, the ideal switching function can be written as a simple arithmetic relationship between the control signals of the switches defined in Figure 1, such that

S_{i} + {\bar{S}}_{i} = 1

(where

i : a, b, o r c

). Consequently, the voltages

V_{a n}, V_{b n}, V_{c n}

can be expressed as follows:

[\begin{matrix} V_{a n} \\ V_{b n} \\ V_{c n} \end{matrix}] = \frac{V_{d c}}{3} [\begin{matrix} 2 & - 1 & - 1 \\ - 1 & 2 & - 1 \\ - 1 & - 1 & 2 \end{matrix}] [\begin{matrix} S_{a} \\ S_{b} \\ S_{c} \end{matrix}]

(1)

2.2. Analytical Modeling of Imperfections

In this section, an analytical model will be developed to consider various imperfections in a 3Ph_VSI. Factors such as dead times between switching signals, switching times, voltage drops caused by power switches (IGBT, SiC, diode), and the effects of parasitic capacitances will be taken into account. The focus of the study is on analyzing one leg of the VSI, as illustrated in Figure 2.

In the following, the distortion voltage due to imperfections is defined as

v_{a n}^{e r r}

, which is the difference between the actual output voltage (

v_{a n}

) and the ideal output voltage (

v_{a n}^{*}

), corresponding to a perfect inverter:

v_{a n}^{e r r} = v_{a n}^{e r r 1} + v_{a n}^{e r r 2} + v_{a n}^{e r r 3} + v_{a n}^{e r r 4} = v_{a n} - v_{a n}^{*}

(2)

where

$v_{a n}^{e r r 1}$ is the average voltage drop over one modulation period (PWM) due to dead times,
$v_{a n}^{e r r 2}$ is the average voltage drop due to component switching times,
$v_{a n}^{e r r 3}$ is the average voltage drop due to voltage drops across power switches,
$v_{a n}^{e r r 4}$ is the average voltage drop caused by the effects of parasitic capacitances.

2.2.1. Dead time effect

Ideally, based on Figure 2, the power switches S1 and S4 are controlled by PWM signals (

S_{H}

S_{L}

). In reality, a dead time (

t_{d}

) needs to be introduced where both S1 and S4 turn off at the same time to prevent a short circuit from occurring through S1 and S4. During the dead time interval, the phase current flows through diode D4, resulting in an output voltage equal to

- \frac{V_{d c}}{2}

when the current is positive (

i_{a} > 0

). When the current is negative (

i_{a} < 0

), the phase current flows through diode D1, causing the output voltage to become positive

\frac{V_{d c}}{2}

. The average voltage drop caused by the dead time (the yellow area in Figure 3) can be expressed as follows:

v_{a n}^{e r r 1} = Δ V_{1} s i g n (i_{a}) w i t h Δ V_{1} = - V_{d c} (\frac{t_{d}}{T_{s}})

(3)

The relation (3) demonstrates that the average voltage drop induced by the dead time is proportional to the ratio

\frac{t_{d}}{T_{s}}

. When the PWM frequency is increased (

T_{s}

is decreased), the voltage drop becomes more significant if the dead time cannot be reduced in the same proportion due to limitations imposed by the drivers or the power switches (IGBT or SiC). The average distortion voltage at the terminals of phase "a" induced by the dead time can be expressed, based on equation (3), according to the directions of the three phase currents, as follows:

v_{a N}^{e r r 1} = \frac{Δ V_{1}}{3} [\begin{matrix} 2 & - 1 & - 1 \end{matrix}] [\begin{matrix} s i g n (i_{a}) \\ s i g n (i_{b}) \\ s i g n (i_{c}) \end{matrix}]

(4)

2.2.2. Rise time and down time effect

The switching of power electronic components is not instantaneous. In practice, it takes a certain amount of time for a switch to turn on and a certain amount of time to ensure its blocking. These switching times accumulate with the dead time defined in the previous section and must be considered to accurately determine the waveform of the voltage

V_{a n}

. Therefore, when

i_{a} > 0

, the average voltage drop induced by the switching times

t_{o n}

(green area in Figure 3) and

t_{o f f}

(red area in Figure 3) can be expressed as follows:

v_{a n}^{e r r 2} = Δ V_{2} s i g n (i_{a}) w i t h Δ V_{2} = - V_{d c} (\frac{t_{o n} - t_{o f f}}{T_{s}})

(5)

Where:

t_{o n}

is the turn-on time (

t_{o n_{d}} + t_{r}

), with

t_{o n_{d}}

being the propagation time at turn-on, and

t_{r}

being the rise time (from

10 % I_{c}

90 % I_{c}

t_{o f f}

is the turn-off time (

t_{o f f_{d}} + t_{f}

), with

t_{o f f_{d}}

being the propagation time at turn-off, and

t_{f}

being the fall time (from

90 % I_{c}

10 % I_{c}

From equation (5), the voltage drop across phase "a" induced by the switching times can be expressed based on the directions of the three phase currents as follows:

v_{a N}^{e r r 2} = \frac{Δ V_{2}}{3} [\begin{matrix} 2 & - 1 & - 1 \end{matrix}] [\begin{matrix} s i g n (i_{a}) \\ s i g n (i_{b}) \\ s i g n (i_{c}) \end{matrix}]

(6)

2.2.3. Consideration of voltage drops in components

In power electronic systems, voltage drops across components like power switches (IGBT, SiC) and diodes should be taken into account. These voltage drops depend on the direction of the phase current. Let

V_{S W}

represent the voltage drop across a conducting switch, identified by the blue area in Figure 3. With this in mind, the following relationship can be formulated:

v_{a n} = \frac{V_{d c}}{2} - V_{S W}

(7)

With

V_{S W} = V_{s w 0} + R_{s w_{o n}} | I_{a} |

, which represents the voltage drop across the conducting switch, where

V_{s w 0}

is the forward voltage drop of the switch and

R_{s w_{o n}}

is the on-state resistance of the switch. When calculating the voltage drop, the current

| I_{a} |

is assumed to remain constant over a PWM period. As illustrated in Figure 3 when

i_{a} > 0

and

G_{H}

is in a low state while

G_{L}

is in a conducting state, the current then flows through diode D4. During this conduction phase, the output voltage

v_{a n}

takes the following value:

v_{a n} = \frac{V_{d c}}{2} - V_{F D}

(8)

With

V_{F D} = V_{F 0} + r_{f} | I_{a} |

, which represents the voltage drop across the conducting diode, where

V_{F 0}

is the forward voltage drop of the diode and

r_{f}

is the on-state resistance of the diode. When calculating the voltage drop, the current

| I_{a} |

is assumed to remain constant over a PWM period. By combining the both terms, the average output voltage drop resulting from the voltage drops in the components can be rewritten as a function of the sign of the current in the corresponding phase (in this case, phase a).

v_{a n}^{e r r 3} = Δ V_{3} s i g n (i_{a}) w i t h Δ V_{3} = - (V_{S W} . D + V_{F D} . (1 - D))

(9)

The average voltage drop across phase "a" induced by the voltage drops in the components can be expressed in terms of the directions of the three-phase currents as follows:

v_{a N}^{e r r 3} = \frac{Δ V_{3}}{3} [\begin{matrix} 2 & - 1 & - 1 \end{matrix}] [\begin{matrix} s i g n (i_{a}) \\ s i g n (i_{b}) \\ s i g n (i_{c}) \end{matrix}]

(10)

2.3. Effects of Parasitic Capacitance

Power semiconductor models (IGBT, SiC) exhibit parasitic capacitances, particularly the output capacitance between the emitter and collector for IGBTs, and between the drain and source for SiC, as shown in Figure 2. These capacitances, with values around a few nF, influence switching and affect output voltage distortion during dead times, depending on the switch type (IGBT or SiC), and also include wiring parasitic capacitances.

In Figure 4, when the phase current flows in the positive direction, during the on period (S1 is ON), the phase current flows through S1. Then the voltage across the inverter becomes

V_{a n} = \frac{V_{d c}}{2}

and the bottom parasitic capacitance (

C_{4}

) is charged. During the dead time interval, the top parasitic capacitance (

C_{1}

) starts charging and

C_{4}

discharges to let the phase current flow. Thus, the voltage across the inverter becomes

V_{a n} = {- \frac{V_{d c}}{2} + V}_{C 4}

. Then,

C_{4}

discharges and the voltage of

C_{4}

(

V_{C_{4}}

) reaches zero (

V_{a n} = - \frac{V_{d c}}{2}

). At this point, the phase current (

i_{a}

) can be expressed as the sum of the charge current (

i_{C_{1}}

) and the discharge current (

i_{C_{4}}

). Assuming that

C_{1}

C_{4}

are equal (

C_{1} = C_{4} = C_{o u t}

), where

C_{o u t}

is the total parasitic capacitance, which depends on both the transistor parasitic capacitance and the external capacitance due to the cable’s connection. The charge or discharge time (

t_{c d}

) of the parasitic capacitor is represented by:

t_{c d} = \frac{2 C_{o u t} (V_{d c} - V_{s w} + V_{F D})}{|i_{a}|}

(11)

The current for charging (or discharging) the capacitance in the actual dead time interval (

t_{d} + t_{o n} - t_{o f f}

) of Figure 4 is called the threshold current (

I_{t h}

) and is given by:

I_{t h} = \frac{2 C_{o u t} (V_{d c} - V_{s w} + V_{F D})}{t_{d} + t_{o n} - t_{o f f}}

(12)

Three situations where the absolute value of the phase current (

i_{a}

) is more than

I_{t h}

(

| i_{a} | > I_{t h}

, brown line), equal to

I_{t h}

(

| i_{a} | = I_{t h}

, purple line) and less than

I_{t h}

(

| i_{a} | < I_{t h}

, red line), are illustrated by Figure 4.

The orange areas of Figure 3 shows the voltage drop caused by the parasitic capacitors, then considered as expressions obtained as a function of the phase current [9,10,11,12].

When

i_{a} > 0

(1): if $| i_{a} | < I_{t h}$ ;

$Δ V_{a n}^{e r r 4} = \frac{t_{d c}}{T_{S}} [(V_{d c} - V_{s w} + V_{F D}) - \frac{|i_{a}| t_{c d}}{4 C_{o u t}}]$

(13)
(2): if $| i_{a} | = I_{t h}$ ;

$Δ V_{a n}^{e r r 4} = \frac{t_{c d} (V_{d c} - V_{S W} + V_{F D})}{2 T_{s}}$

(14)
(3): if $| i_{a} | > I_{t h}$ ;

$Δ V_{a n}^{e r r 4} = \frac{C_{o u t} {(V_{d c} - V_{S W} + V_{F D})}^{2}}{T_{s} |i_{a}|}$

(15)

The average voltage drop due to parasitic capacitances,

V_{a n}^{e r r 4}

, can be rewritten as a function of the sign of the current in the corresponding phase (in this case, phase a).

v_{a n}^{e r r 4} = Δ V_{4} s i g n (i_{a})

(16)

with

Δ V_{4} = \{\begin{matrix} \frac{t_{c d}}{T_{s}} ((V_{d c} - V_{s w} + V_{F D}) - \frac{| i_{a} | t_{c d}}{4 C_{o u t}}), & | i_{a} | < I_{t h} \\ \frac{C_{o u t}}{T_{s} | i_{a} |} {(V_{d c} - V_{s w} + V_{F D})}^{2}, & | i_{a} | \geq I_{t h} \end{matrix}

(17)

In a general sense, the amplitude of the threshold current (

I_{t h}

) is much lower than the phase current magnitude

| i_{a} |

. As a result, the relationship (17) can be simplified as follows:

Δ V_{4} = \frac{C_{o u t}}{T_{s} | i_{a} |} {(V_{d c} - V_{s w} + V_{F D})}^{2}, i_{a} \neq 0

(18)

The variations of

v_{a N}^{e r r 4}

with respect to the values taken by the phase current

i_{a}

are then represented in green in Figure 5 (curve in

\frac{1}{| i_{a} |}

for

| i_{a} | \geq I_{t h}

). The voltage drop caused by other imperfections,

V_{a n}^{e r r 1, 2, 3}

(dead times, switching times, and voltage drop in components), is also depicted in red on this figure, along with the resulting voltage drop shown in blue. It can be observed that the parasitic capacitances have a beneficial effect on the voltage drop, leading to lower values, but this depends on the magnitude of the load current.

Figure 6 shows the impact of the parasitic capacitance value on the overall voltage drop (limited to

i_{a} > 0

). A larger parasitic capacitance limits the voltage drop for low currents, but it has little effect on the average global voltage drop at the inverter output for higher currents.

The average voltage drops resulting from different imperfections of the inverter have been derived in this section. Consequently, the total voltage drop across phase "a" can be expressed as follows:

v_{a N}^{e r r 4} = \frac{Δ V}{3} [\begin{matrix} 2 & - 1 & - 1 \end{matrix}] [\begin{matrix} s i g n (i_{a}) \\ s i g n (i_{b}) \\ s i g n (i_{c}) \end{matrix}]

(19)

where

Δ V = Δ V_{1} + Δ V_{2} + Δ V_{3} + Δ V_{4}

(20)

Finally, based on equation (1), this voltage drop can be expressed for all three phases, depending on the signs of the respective currents.

[\begin{matrix} v_{a N}^{e r r} \\ v_{b N}^{e r r} \\ v_{c N}^{e r r} \end{matrix}] = \frac{Δ V}{3} [\begin{matrix} 2 & - 1 & - 1 \end{matrix}] [\begin{matrix} s i g n (i_{a}) \\ s i g n (i_{b}) \\ s i g n (i_{c}) \end{matrix}]

(21)

3. The influence of imperfections on the output voltage of the inverter

The previous section discussed the average voltage drops resulting from imperfections in the inverter. These imperfections will have two key effects. Firstly, there will be a voltage drop in the RMS value of the fundamental component of the inverter’s output voltage. Secondly, the imperfections will generate additional voltage harmonics that will affect the load current, especially the low-frequency harmonics. These effects will be further examined in the following section.

3.1. RMS value of the fundamental component of the output voltage

The RMS value of the fundamental component at the terminals of a phase (

V_{a N 1}

) can be derived by considering the modulation index (

m_{a}

) and the DC bus voltage (

V_{d c}

V_{a N 1} = \frac{V_{d c}}{2 \sqrt{2}} m_{a}

(22)

In the case of an inductive load with a phase lag of

ϕ_{1}

, the RMS value of the distortion in the phase voltage

V_{a N}^{e r r} (t)

can be expressed as follows:

V_{a N 1}^{e r r} = \frac{4 Δ V}{π \sqrt{2}}

(23)

Where the term

Δ V

has been defined in equation (20) and encompasses all the voltage drops resulting from the imperfections of the inverter. The value of the voltage drop

V_{a N 1}^{e r r}

can be evaluated based on the measurement of

V_{a 1}

V_{a N 1}^{e r r} = \frac{- 2 V_{a 1} cos ϕ \pm \sqrt{{(2 V_{a 1} cos ϕ)}^{2} + 4 (V_{a_{ref}}^{2} - V_{a 1}^{2})}}{2}

(24)

The voltage

V_{a_{r e f}} (t)

represents the fundamental component of the voltage across phase "a" that would occur in the absence of any imperfections.

3.2. Harmonics generated by the inverter’s imperfections

The literature focuses on the impact of dead times on harmonic amplitudes, leading to complex formulas [13,14,15]. Dead times increase harmonics and decrease the fundamental. THD of output voltage increases linearly with dead time. Dead times also generate low-frequency harmonics, harder to filter and harmful for synchronous machines [16]. The presence of these low-frequency harmonics is explained based on the voltage

V_{a N}^{e r r} (t)

and its spectral decomposition is given by:

V_{a N}^{e r r} (t) = \frac{4}{π} Δ V \sum_{n = 1}^{\infty} \frac{1}{n} sin (n ω_{1} t)

(25)

where

Δ V

is defined in equation (20), n represents the harmonic order (

n = 5, 7, 11, 13, . . .

), and

ω_{1}

is the fundamental frequency. The following relationship is obtained through the development of calculations:

\begin{matrix} v_{a N} (t) & = \frac{V_{d c}}{2 m_{a}} sin (ω_{1} t + ϕ) + V_{a N}^{e r r} (t) \\ = [\frac{V_{d c}}{2 m_{a}} sin (ω_{1} t + ϕ) + \frac{4}{π} Δ V sin (ω_{1} t)] + \frac{4}{π} Δ V [\frac{1}{5} sin (5 ω_{1} t) + \frac{1}{7} sin (7 ω_{1} t) + \dots] \end{matrix}

(26)

Low-frequency harmonics will be introduced into the voltage across the load due to inverter imperfections. In the following section, these low-frequency harmonics will be experimentally demonstrated.

4. Experimental results

To confirm the validity of our study, experimental tests were conducted on three different switches, including two IGBTs and one SiC MOSFET. The parameters of the switches are provided in Table 1. Table 2 presents the specification of the 3Ph-VSI.

The test bench is consists of the 3Ph-VSIs, a TDK Lambda 600V, 6000W DC source, a power analyzer Tektronix

P A 4000

, a dSPACE MicroLabBox to control the system, a three-phase RL load (

0 - 50 Ω

, 3mH) and a 100 MHz Rohde & Schwarz oscilloscope. The test bench is depicted in Figure 7.

Achieving a high switching frequency (beyond 40 kHz) utilizing the Matlab / Simulink / dSPACE RTI approach proved unattainable. Consequently, an alternative course was pursued by employing C language programming and dSPACE RTLib [17] to program the MicroLabBox. The vector control routine finds its implementation within an Interrupt Service Routine (ISR) operating at half of the switching frequency. In order to facilitate meticulous comparisons, open loop tests were conducted, entailing the application of constant reference voltages.

4.1. Analysis of switching events for the SiC-MOSFET inverter

Figure 8 displays the measurements obtained for the SiC-MOSFET inverter with a dead time (

t_{d}

) set at

2.5 μ s

during the turn-on of switch

S_{a H}

. The measurements were taken for various current values at the time of switching (positive or negative current).

Figure 8 shows the conduction of switch

S_{a H}

and the blocking of switch

S_{a L}

. The gate control signals change, affecting the voltage of the

C_{4}

(

V_{C_{4}}

see Figure 2) depending on the current direction and magnitude during switching. High negative currents cause a rapid

V_{C_{4}}

rise, while lower currents slow it down. A specific case matches

V_{C_{4}}

rise time with the dead time. Positive currents result in a

V_{C_{4}}

jump after the dead time due to switch

S_{1}

activation. These results align with the theoretical study.

The theoretical studies were validated by reducing the dead time from

2.5 μ s

1.5 μ s

. The results in Figure 9 show that, at low current values (cyan curves), the parasitic capacitance cannot be fully charged or discharged before the end of the dead time, resulting in a voltage

V_{C_{4}}

discontinuity during switching.

4.2. Measurement of the value of parasitic capacitances

The relationship between

C_{o u t}

(assumed

C_{o u t} = C_{1} = C_{4}

), the constant current magnitude

| I_{a} |

at switching, the discharge time (

Δ t

), and the voltage variation (

Δ V

) across the component can be expressed as follows:

C_{o u t} = \frac{Δ t | I_{a} |}{2 Δ V}

(27)

The curves in Figure 10 (a) for SiC-MOSFET, Figure 10 (b) for IGBT1, and Figure 10 (c) for IGBT2 were used to determine

C_{o u t}

for each inverter. The discharge time, voltage variation, and current magnitude at switching were recorded from the cyan-colored curves. It was observed that the voltage variation appeared to be linear for the SiC and IGBT2 inverters, consistent with model assumptions. However, for the IGBT1 inverter, the slope increased at lower voltages. Although some studies suggest an increase in parasitic capacitance with decreasing voltage, this phenomenon will be disregarded to maintain a simple model.

The impact of parasitic capacitances on the voltage drop and model accuracy was studied. Figure 11 shows the voltage drop evolution with PWM frequency for three different dead time values. The theoretical curves were plotted with and without parasitic capacitance effects and compared to PA4000 measurements.

Neglecting parasitic capacitances in the modeling leads to an evident overestimation of the voltage drop, averaging around 15%. Considering these capacitances allows for highly accurate voltage drop estimation when compared to actual measurements. Thus, ignoring this phenomenon hampers correct prediction of a three-phase inverter’s output voltage value.

4.3. Comparison of the performances of the 3 inverters

The SiC-MOSFET inverter exhibits the highest voltage drop, followed by the IGBT2 inverter, and then the IGBT1 inverter (Figure 12). The SiC-MOSFET inverter’s voltage drop can be significantly reduced by setting the dead time to

0.5 μ s

, which is not feasible for IGBT1 and IGBT2 due to their substantial blocking time (around

600 n s

). In conclusion, a low dead time is crucial when increasing the PWM frequency for some applications such as high-speed electric motors to avoid significant voltage drop. However, IGBT inverters are limited to approximately

1 μ s

of dead time due to their blocking times, which restricts their use for high-frequency drives. Increasing the DC bus voltage to compensate for the voltage drop is possible, but often limited by other constraints. Control strategies that compensate for dead time effects exist, but they are beyond the scope of this thesis.

The harmonic spectra of phase voltage (

V_{a N}

) were obtained experimentally and using the analytical model concerning the dead time (

t_{d}

) and different modulation frequency index values (

m_{f}

). From these results, it can be observed that the fundamental value decreases with an increase in PWM frequency (increase in

m_{f}

). However, the amplitudes of the different harmonics remain nearly constant regardless of the value of

m_{f}

4.4. Measurement of the total harmonic distortion of voltage for the 3 types of inverters

The decrease in the fundamental value with

m_{f}

, while the amplitudes of the different harmonics remain constant, leads to an increase in

T H D_{v}

with the PWM frequency for a given dead time. This observation is further supported by the

T H D_{v}

measurement results shown in Figure 13. For instance, when comparing the

T H D_{v}

value for

t_{d} = 2 μ s

, it increases from

100 %

f_{s} = 10 k H z

to approximately

117 %

f_{s} = 40 k H z

Figure 14 compares the measurement results of

T H D_{v}

for the 3 inverters under the same operating conditions. These results demonstrate that the

T H D_{v}

is consistently highest for the SiC-MOSFET inverter. However, selecting a very low dead time, which is possible with this type of component, can significantly improve

T H D_{v}

. We conducted a

T H D_{v}

measurement for the SiC-MOSFET inverter by setting the dead time to

0.5 μ s

. The results are shown in Figure 14, indicating that the

T H D_{v}

remains at

95 %

regardless of the PWM frequency value.

As mentioned earlier, low-frequency voltage harmonics (5^th, 7^th orders, etc.) arise due to dead times. While their impact on voltage remains relatively minor in comparison to PWM-induced harmonics, they gain significance in the current waveform due to the role of the R-L load as a low-pass filter. Various dead times (ranging from

0.5 μ s

5 μ s

) were tested on a SiC-MOSFET inverter operating with a 400 Hz fundamental frequency and 20 kHz PWM frequency (modulation factor,

m_{f} = 50

). Figure 15 illustrates the results with the fundamental current amplitude normalized to

0.5

A (the current value is

4.1

A). The increase in dead time amplifies the 5^th and 7^th order harmonics, overshadowing the PWM-related harmonics around the 50^th order. A near-linear correlation between the amplitude of the 5^th and 7^th harmonics and the dead time is evident from the findings in Figure 15. The amplitude of the

n^{t h}

-order harmonic (where

n = 5, 7, 11, 13, \dots

) for the current passing through the

R - L

load is governed by the following equation:

I_{n} = \frac{4}{π n} \cdot \frac{V_{d c}}{\sqrt{R^{2} + {(L n ω_{1})}^{2}}} \cdot \frac{t_{d}}{T_{s}}; n = 5, 7, 11, 13, \dots

(28)

This relationship underscores the direct proportionality between

I_{n}

and the dead time value

t_{d}

, as corroborated by experimental observations. Applying Equation (28) using the parameter values from Table 1 and adopting

R = 27.3 Ω

and

L = 3

mH, which corresponds to the experiments in Figure 15, yields an

I_{5}

value of

0.306

A for

t_{d} = 5 μ s

. This outcome closely aligns with the experimentally recorded value of approximately

0.3

5. Conclusions

This paper introduces an analytical model for a three-phase inverter, encompassing factors such as dead times, switching times, voltage drops across components, and parasitic capacitance. The model effectively forecasts the voltage drop at the fundamental frequency of the inverter’s output voltage. Overlooking parasitic capacitance may result in an overestimation of this voltage drop. Among the contributors, dead times stand out as the primary cause of the most substantial voltage drop, influencing low-frequency harmonics that affect the load current.

The proposed model’s validity is established through experimental trials conducted on three-phase inverters equipped with distinct power components (IGBT and SiC MOSFET). The results demonstrate that the SiC inverter displays a greater voltage drop compared to IGBT-based inverters under identical dead time conditions. Nonetheless, the SiC inverter can significantly diminish the dead time to 0.5 µs, leading to a reduced voltage drop. The model consistently predicts the inverter’s output voltage drop and Total Harmonic Distortion (THD), with THD reduction at higher frequencies when minimizing dead time in the SiC-MOSFET inverter.

Furthermore, the impact of dead time on low-frequency harmonics is explored and verified through experimental tests, highlighting the significant influence of these harmonic amplitudes on THD. This emphasizes their role in shaping THD and underscores their importance in practical applications.

References

Lin, Z.; An, Q.; Xie, C. SiC-Based Inverter Fed High-Speed Permanent Magnet Synchronous Motor Drive. 5th Asia Conference on Power and Electrical Engineering (ACPEE), 2020, pp. 1300–1304. [CrossRef]
Allca-Pekarovic, A.; Kollmeyer, P.J.; Mahvelatishamsabadi, P. Comparison of IGBT and SiC Inverter Loss for 400V and 800V DC Bus Electric Vehicle Drivetrains. IEEE Energy Conversion Congress and Exposition (ECCE), 2020, pp. 6338–6344. [CrossRef]
Perdikakis, W.; Scott, M.; Kitzmiller, C.; Yost, K.J. Comparison of Si and SiC EMI and Efficiency in a Two-level Aerospace Motor Drive Application. IEEE Transactions on Transportation Electrification, 1401. [Google Scholar] [CrossRef]
Kapino, G.; Franke, W. Loss Comparison for Different Technologies of Semiconductors for Electrical Drive Motor Application. IEEE 13th International Conference on Compatibility, Power Electronics and Power Engineering (CPE-POWERENG), 2019. [CrossRef]
Qi, F.; Wang, M.; Xu, L. Investigation and Review of Challenges in A High Temperature 30 kVA 3 phase inverter using SiC MOSFETs. IEEE Transactions on Industry Applications, 2483. [Google Scholar] [CrossRef]
Shenoy, P.; Solis, O.; Zheng, L. Commercializing medium voltage VFD that utilizes high voltage SiC technology. IEEE International Workshop On Integrated Power Packaging (IWIPP), 2017. [CrossRef]
Nawawi, A.; Tong, C.F.; Yin, S.; Sakanova, A. Design and Demonstration of High Power Density Inverter for Aircraft Applications. IEEE Transactions on Industry Applications, 1168. [Google Scholar] [CrossRef]
Han, D.; Li, Y.; Sarlioglu, B. Analysis of SiC Based Power Electronic Inverters for High-Speed Machines. IEEE Applied Power Electronics Conference and Exposition (APEC), 2015, pp. 304–310. [CrossRef]
Ding, X.; Du, M.; Duan, C.; Guo, H.; Xiong, R.; Xu, J.; Cheng, J.; Luk, P. Analytical and Experimental Evaluation of SiC-Inverter Nonlinearities for Traction Drives Used in Electric Vehicles. IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY. [CrossRef]
Bedetti, N.; Calligaro, S.; Petrella, R. Self-Commissioning of Inverter Dead-Time Compensation by Multiple Linear Regression Based on a Physical Model. IEEE Applied Power Electronics Conference and Exposition - APEC 2014, 2015, 3954–3964. [Google Scholar]
Bedetti, N.; Calligaro, S.; Petrella, R. Accurate modeling, compensation and self-commissioning of inverter voltage distortion for high-performance motor drives. IEEE Transactions on Industry Applications, 1550. [Google Scholar] [CrossRef]
Dafang, W.; Peng, Z.; Yi, J.; Miaoran, W.; Gang, L.; Mingyu, W. Influences on Output Distortion in Voltage Source Inverter Caused by Power Devices’ Parasitic Capacitance. IEEE Transactions on Power Electronics, 4261. [Google Scholar] [CrossRef]
Holmes, D.G.; Lipo, T.A. Modulation of Three-Phase Voltage Source Inverters. In Pulse Width Modulation for Power Converters: Principles and Practice; IEEE: New York City, NY, USA, 2003; pp. 215–258. [Google Scholar]
Wu, C.M.; Lau, W.h.; Chung, H.S.h. Analytical Technique for Calculating the Output Harmonics of an H-Bridge Inverter with Dead Time. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 1999, 46, 617–627. [Google Scholar] [CrossRef]
Deng, H.; Helle, L.; Bo, Y.; Larsen, K.B. A general solution for theoretical harmonic components of carrier-based PWM schemes. Proc. of the APEC 2009, 15-19 Feb. 2009, 2009, 1698–1703. [Google Scholar]
Kus, V.; Josefova, T. The Influence of the Dead Time Duration and Switching Frequency on the Input Current Distortion of Voltage-Source Active Rectifiers. International Conference on Applied Electronics (AE) 2015, 08-09 September 2015, 2015, 1–4. [Google Scholar]
Baghli, L.; Jamshidpour, E. Implementing a 200 kHz PWM Field Oriented Control using RTLib and C program on a dSPACE MicroLabBox. 2022 2nd International Conference on Advanced Electrical Engineering (ICAEE), 2022, pp. 1–6. [CrossRef]

Figure 1. Three-phase Voltage Source Inverter.

Figure 2. A-phase leg of three-phase inverter with the dead-time block.

Figure 3. Waveform of the output voltage taking into account voltage drops, dead time, switching times and parasitic capacitors.

Figure 4. Effects of Parasitic Capacitance, (a) Switch turn on (b) switch turn off.

Figure 5. The average voltage drop due to parasitic capacitances as a function of

i_{a}

is shown in the green curve, and the overall voltage drop (global voltage drop) is represented by the blue curve.

Figure 5. The average voltage drop due to parasitic capacitances as a function of

i_{a}

is shown in the green curve, and the overall voltage drop (global voltage drop) is represented by the blue curve.

Figure 6. Effect of parasitic capacitance value on the output voltage drop.

Figure 7. Experimental test bnch.

Figure 8. The voltage across a switch during the dead time is measured for different current levels and

t_{d} = 2.5 μ s

in the SiC-MOSFET inverter.

Figure 8. The voltage across a switch during the dead time is measured for different current levels and

t_{d} = 2.5 μ s

in the SiC-MOSFET inverter.

Figure 9. The voltage across a switch during the dead time is measured for different current levels and

t_{d} = 1.5 μ s

in the SiC-MOSFET inverter.

Figure 9. The voltage across a switch during the dead time is measured for different current levels and

t_{d} = 1.5 μ s

in the SiC-MOSFET inverter.

Figure 10.

V_{C_{o u t}}

of (a) the SiC-MOSFET inverter, (b) the IGBT1 inverter, (c) the IGBT2 inverter.

Figure 10.

V_{C_{o u t}}

of (a) the SiC-MOSFET inverter, (b) the IGBT1 inverter, (c) the IGBT2 inverter.

Figure 11. The voltage drop

V_{a N 1}^{e r r}

of the SiC inverter as a function of the PWM frequency for three different values of dead time.

Figure 11. The voltage drop

V_{a N 1}^{e r r}

of the SiC inverter as a function of the PWM frequency for three different values of dead time.

Figure 12. Comparison of the voltage drop for the 3 types of inverters.

Figure 13. The variation of

T H D_{v}

(Total Harmonic Distortion of voltage) for the SiC MOSFET inverter concerning dead time and at different modulation frequency indices

m_{f}

Figure 13. The variation of

T H D_{v}

(Total Harmonic Distortion of voltage) for the SiC MOSFET inverter concerning dead time and at different modulation frequency indices

m_{f}

Figure 14. Comparison of the

T H D_{v}

(Total Harmonic Distortion of voltage) for the SiC-MOSFET, IGBT1, and IGBT2 inverters, varying with dead time and at different PWM frequencies.

Figure 14. Comparison of the

T H D_{v}

(Total Harmonic Distortion of voltage) for the SiC-MOSFET, IGBT1, and IGBT2 inverters, varying with dead time and at different PWM frequencies.

Figure 15. Experimental measurement of the current spectrum in the R-L load with modulation factor (

m_{f} = 50

) for various dead time (

t_{d}

) values.

Figure 15. Experimental measurement of the current spectrum in the R-L load with modulation factor (

m_{f} = 50

) for various dead time (

t_{d}

) values.

Table 1. Paramètres des composants.

Paramètres	IGBT1	IGBT2	SiC MOSFET
	(SEMiX251GD126HD)	(SKM100GB125DN)	(CCS050M12CM)
$V_{C E}$ ou $V_{D S}$ (V)	1200	1200	1200
$I_{C}$ ou $I_{D}$ (A) à 25ºC	242	100	87
$I_{F}$ (A) à 25ºC	207	95	102
$r_{C E}$ ou $r_{D S (o n)}$ (m $Ω$ )	7	22.5	25
$r_{F}$ (m $Ω$ )	5	11.1	20
$V_{C E 0}$ (V)	0.9	2.3	0
$V_{F 0}$ (V)	1.1	1	1.5
$E_{o n r e f}$ (mJ)	37	11	1.1
$E_{o f f r e f}$ (mJ)	22	4	0.6
$E_{r r r e f}$ (mJ)	12	4	-
$t_{o n}$ (ns)	295	75	51
$t_{o f f}$ (ns)	625	600	69
$R_{G}$ ( $Ω$ )	10	10	20

Table 2. Specifications of the three-phase inverter.

Parameters	Value
DC bus voltage ( $V_{dc}$ )	$> 540$ V
Output current of the inverter ( $I_{eff}$ )	30 Arms
PWM frequency ( $f_{s}$ )	10-100 kHz
Fundamental frequency ( $f_{1}$ )	50-3000 Hz
Efficiency ( $η$ )	$> 90 %$

Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

Copyright: This open access article is published under a Creative Commons CC BY 4.0 license, which permit the free download, distribution, and reuse, provided that the author and preprint are cited in any reuse.

MDPI Initiatives

Important Links

Choose an area of interest and we will send you notifications of new preprints at your preferred frequency.

Disclaimer

Comparative Study of IGBT and SiC MOSFET Three-Phase Inverter: Impact of Parasitic Capacitance on the Output Voltage Distortion

Abstract

1. Introduction

2. Analytical Modeling of a three-phase voltage source inverter and Imperfections

2.1. Three-phase voltage source inverter modeling

2.2. Analytical Modeling of Imperfections

2.2.1. Dead time effect

2.2.2. Rise time and down time effect

2.2.3. Consideration of voltage drops in components

2.3. Effects of Parasitic Capacitance

3. The influence of imperfections on the output voltage of the inverter

3.1. RMS value of the fundamental component of the output voltage

3.2. Harmonics generated by the inverter’s imperfections

4. Experimental results

4.1. Analysis of switching events for the SiC-MOSFET inverter

4.2. Measurement of the value of parasitic capacitances

4.3. Comparison of the performances of the 3 inverters

4.4. Measurement of the total harmonic distortion of voltage for the 3 types of inverters

5. Conclusions

References

MDPI Initiatives

Important Links

Subscribe