A Comparative Study of n- and p- Channel FeFETs with Ferroelectric HZO Gate Dielectric

1. Introduction

Ferroelectric field effect transistors (FeFETs), particularly hafnium oxide (HfO2) based FeFETs, have captured the interest of semiconductor technology as the dominant candidates for future memory applications. FeFETs have all the design components of a traditional MOSFET with a sandwiched ferroelectric material layer as the gate dielectric. The two polarization states of the dielectric determine two separate threshold voltages giving rise to a memory window (MW) between two non-volatile memory states. The discovery of ferroelectricity in hafnium oxide based dielectrics which are CMOS compatible, has attracted enormous interests in integrating FeFETs in emerging non volatile memory, in-memory computing, and neuromorphic computing applications [1,2,3]. This is in conjunction with rapid developments in artificial intelligence (AI) technology, which has put forward the requirements for high-speed, energy efficient, and non-volatile memories [4,5,6]. In this regard, the research community has observed a shift from the existing von Neumann computer architectures, driven by developments in FeFET technology [7,8,9]. FeFETs have demonstrated scalability, low power operation due to their CMOS compatibility, and faster non-destructible read/write operation capabilities.

The ferroelectricity observed in ferroelectric materials is primarily due to their non-centrosymmetric structure [1]. A large number of ferroelectric materials have been reported in the literature, however the most popular ones are PZT, PVDF, and HZO [1]. In such materials the polarization direction is controlled by the displacement of the atoms, their degree of variation in crystalline phase and material compositions [10,11,12,13,14,15,16,17,18,19].

Among the various dopants in hafnium oxide (HfO2) such as Al, Sr, La, Gd, Si, and Zr that enable ferroelectricity, Zr doped HfO2 films have been observed to demonstrate stable ferroelectric behavior over a wide range of temperatures, compositions, and require a lower processing temperature [20,21,22,23,24]. The principle of a FeFET is the change in threshold voltage resulting from the polarization states of the gate dielectric that induce charges at the gate/channel region. Figure 1 depicts the effects of up and down polarization in n-FeFET and p-FeFET and comparing with charge trapping effects which are opposite to the polarization effects [25].

Hafnium oxide based FeFETs, however, may encounter undesirable charge trapping during the program and erase cycles required for polarization switching [1,20,26]. This is due to the defect density in HfO₂, which limits the span of the memory window post program cycles [1,20,26]. Therefore, the devices demonstrate a slower read operation which leads to a departure from the theoretical values of the memory window (MW) [1,27]. This calls for an early assessment of the different kinds of traps that form in the dielectric stack of the fabricated structure and is the focus of this study.

2. Materials and Methods

2.1. Experimental

The FeFETs were fabricated in a student run fab [28] at Rochester Institute of Technology (RIT) on 1-10 Ω-cm base resistivity silicon wafers with 10 nm ALD deposited hafnium zirconium oxide (Hf_0.5Zr_0.5O₂) as the gate dielectric and 15 nm of sputtered TiN as the gate electrode, followed by an anneal at 600˚ C to achieve the ferroelectric phase. The process flow consisted of 5 mask levels designed in-house using Mentor Graphics Pyxis, fabricated by a Heidelberg DWL 66+ direct laser writer, and using the ASML PAS5500 i-line stepper for lithography. The devices consisted of LOCOS (local oxidation of silicon) isolated FETs with ion implanted source and drain regions implanted by the Varian 350D ion implanter. For the n-channel devices, a P31 implant species were used, and for the p-channel devices a B11 implant species were used. The process flow and the device schematics are shown in Figure 2.

A scanning electron micrograph image of a fabricated device (with designed 15 µm channel length and 15 µm channel width) and a high-resolution TEM image of the gate dielectric are shown in Figure 3. A close observation of the TEM image reveals the crystalline nature of the deposited ferroelectric HZO (Hf_0.5Zr_0.5O₂) thin film on the silicon substrate. Further, at the HZO/Si interface, a thin interfacial layer (IL) of SiO_x (~ 1.63 nm) is observed.

2.2. Polarization Characterization of HZO

The HZO layer employed in this work was characterized for its polarization behavior by fabricating MFM capacitors. The fabricated test structure helps in the assessment and characterization of the deposited thin film ferroelectric layers. The layer stack of the MFM capacitor consists of a bottom electrode deposited by sputtering and standard liftoff procedures to realize a 100 nm TiN layer. This is followed by the conformal atomic layer deposition (ALD) of the 10 nm Hf_0.5Zr_0.5O₂ ferroelectric layer. The top electrode, TiN is then deposited by sputtering.

The polarization-electric field (P-E) hysteresis loop of the test structure were recorded with a Keithley 4200 parameter analyzer, illustrated in Figure 4. As observed, the test structure demonstrates good polarization switching behavior with a remanent polarization (2P_R) of 34 μC/cm² and a coercive field (E_C) of 1 MV/cm. Also presented is the calibration of a metal-ferroelectric-metal (MFM) capacitor through Silvaco’s Victory TCAD simulator, which will be used as a primer for realizing the fabricated FeFETs through TCAD for further analysis [29].

3.1. Experimental Results

3.1.1. DC Characterization

To investigate the DC characteristics, Keithley’s 4200-SCS parametric analyzer was used. The transfer characteristics (I_D vs V_GS) for the n- and p-FeFETs are shown in Figure 5. The memory window (MW) specified at the drain current of 1 nA/µm, is observed to be 1 V for the n-FeFET and 1.4 V for the p-FeFET. The DC characteristics of the n- and p-FeFETs demonstrate asymmetric subthreshold characteristics. The p-channel devices exhibit steeper subthreshold characteristics compared to their n-channel counterparts. In addition, the n-FeFETs demonstrate a higher contribution of the gate-induced-drain-leakage (GIDL) current component, suggesting the role of stronger band bending at the accumulation region which is responsible for the setup of high electric fields. This consequently results in the tunneling of the valence band (VB) electrons to the conduction band (CB) while generating holes in the VB, otherwise known as band-to-band tunneling (BTBT). Another distinguishing feature of the n-FeFETs is the characteristic crossover point observed during the downward sweep in the transfer characteristics.

3.1.2. Pulse Characterization

The fabricated n- and p-channel FeFET devices were characterized through a series of read and write pulse cycles using a FormFactor Cascade Microtech Summit 11000/12000 probe station & Keithley 4200-SCS parametric analyzer. The pulse setups for the n- and p-channel devices are shown in Figure 6. For the n-channel devices, the height of the reset pulse is set to -4.5 V with a pulse duration of 1 µs, while the set pulse height is varied from 1 V to 3.8 V and the pulse duration is gradually tuned from 50 ns to 0.1 s. The p-channel devices are also subjected to similar pulsing conditions with reversed polarities.

The shift in the threshold voltage (V_TH) and the resulting MW for the n- and p-channel devices as a function of pulse width is shown in Figure 7. The switching of the polarization dipoles of a particular ferroelectric layer is a function of both the applied bias and the time duration during which the pulse is applied to the ferroelectric gate stack. As observed from Figure 7a,c, the V_TH of both devices can be tuned gradually by varying both the pulse height and the pulse duration. As the pulse height decreases, a longer pulse is required for observing the necessary switching of the polarization dipoles. For the n-channel FeFETs, a maximum MW of 1 V, is achieved with a pulse height of 3.8 V and pulse duration of 1 µs, as seen in Figure 7b. This point corresponds to the complete switching of the polarization dipoles within the ferroelectric layer. Intermediate pulse height/widths can be utilized for partial polarization in multi-level logic devices. For the p-channel devices, however, the pulse characteristics in Figure 7c,d demonstrate a global maxima in the MW at a pulse duration of 10 µs and a pulse height of -3.8 V. Further, on increasing the pulse width, a characteristic roll-off in the MW is observed as a function of write pulse width.

The switching behavior investigated using different program/erase pulse heights and widths shows a faster complete polarization switching in n-FeFETs (3.8 V, 1 µs) than in p-FeFETs (-3.8 V, 10 µs).

3.2. Simulation Methodology

The polarization parameters extracted from the test structure's P-E hysteresis loops are fed to the simulation deck to realize ferroelectricity in the HZO. The calibrated simulation deck acts as a primer for realizing FeFET devices for the assessment of the trapping parameters. Table 1 provides the geometrical parameters of the fabricated devices used in simulations.

Silvaco’s Victory Device simulator is used to identify the different kinds of traps that evolved during the fabrication process [26]. A detailed simulation methodology is presented to capture the switching of the polarization dipoles during the upward and downward sweeps.

3.2.1. Calibration of the Fabricated Devices

In modeling the fabricated devices, p-channel devices are considered first due to their steeper subthreshold characteristics and a parallel memory window. The off-state current is tuned by considering donor type bulk traps in the silicon substrate. The bulk trap density is set as 1x10¹⁶ cm³ and the trap level is 0.63 eV. The capture cross section for electrons and holes are set to 10^-13 cm² and 10^-14 cm² respectively in accordance with experimental reports [1,20,30]. Further, the literature survey suggests the role of fixed charges and charge trapping at the HZO/SiO₂ interfacial layer (IL) interface in modulating the subthreshold characteristics and thus limiting the memory window of the fabricated devices [1,20,30]. Accordingly, acceptor type interface traps were tuned at the HZO/IL interface to obtain a best fit to the experimental data. In this regard, an interface trap density of 1.8x10¹³ cm², trap energy level of 0.20 eV and capture cross sections of 10^-13 cm² and 10^-14 cm² for electrons and holes respectively were defined at the HZO/IL interface [31]. In addition to these, Fermi and SRH models were invoked to capture carrier statistics and the interaction of carriers with traps that evolved during the fabrication process. The Priesach Ferroelectric model was also invoked to model the doping dependent mobility, CVT model [32] and to capture the ferroelectric polarization. The calibrated simulation deck for the p-channel device was then used as the basis for realizing n-channel FeFETs. The off-state current was tuned again by considering the donor type bulk traps in the silicon substrate. The trapping conditions defined in the substrate were similar to that of p-channel devices in order to mimic similar bulk conditions, except that the OFF–state current was tuned by changing the energy of the trap level to 0.43 eV. The interface trap density at the HZO/IL interface was similar to the p-channel case, except that the trap levels were tuned to 0.26 eV to capture the slow subthreshold characteristics observed in Figure 5a for n-FeFETs. In addition to this, to capture the GIDL effect observed in n-FeFETs, as seen in Figure 5a, Kane’s BTBT model was invoked, and its coefficients were tuned to achieve the best fit to the GIDL current [27]. The calibrated simulation decks for the n- and p-channel devices are shown in Figure 8.

It is observed that the subthreshold characteristics of n-FeFETs are more affected due to charge trapping at the HZO/SiO₂(IL) interface suggesting that electrons are more easily trapped than holes. The presence of IL further participates in a tunneling current, due to charge trapping at the HZO/SiO₂ (IL). This results in a charge transfer directly between the HZO and Si channel and is responsible for modulating the subthreshold characteristics of the n-FeFETs.

The characteristic crossover point observed in the n-channel devices during the downward sweep was also captured in the TCAD simulations, as shown in Figure 8a. A closer insight into this reveals that there is a temporary switching of the ferroelectric based operation to the charged based operation, which arises due to the presence of the fixed charges and charge trapping at the HZO/IL interface and HZO bulk layer.

The devices are further investigated by recording the contour plots of electron/hole concentrations and conduction current densities after forward and reverse sweeps at 1 nA/µm. These are depicted in Figure 9a for n-FeFETs and in Figure 9b for p-FeFETs. For the n-channel device, as observed from Figure 9a, the shift in electron concentration and conduction current density is not significant after the respective program/erase cycles. In contrast, for the p-channel device, a significant change in both the hole concentration as well as the conduction current density is observed in Figure 9b, which accounts for the shift in V_TH observed in both Figure 7c,d and Figure 5b after subjecting the gate stack to the necessary program cycle.

The trapping effects on the MW can be understood by observing the band diagrams recorded at erase and program conditions. This is shown in Figure 10a,b for the n-and p-channel devices, respectively. For the n-FeFET devices, as depicted in Figure 10a, the carriers can directly tunnel through the HZO and the IL (SiO₂) through Fowler-Nordheim (FN) tunneling [33]. The carriers can also participate in tunneling with the help of acceptor type traps defined at the HZO/IL interface and at the HZO bulk through the trap-assisted tunneling (TAT) [33]. The injected carriers are ‘hot’, in the sense that these carriers are energetic and can further participate in the generation of interface traps at the SiO₂ (IL)/Si interface, thereby degrading the quality of the memory window or the devices over time. Consequently, there is a charge sharing directly between the HZO and the silicon channel, which is responsible for modulating the subthreshold characteristics observed in Figure 5a and Figure 8a. Under the program cycle, as depicted in Figure 10b, the electron carriers tunnel through the SiO₂ layer, which is translated to the shift observed in the device threshold voltage. Further, on observing the position of the traps with respect to the fermi level under both erase and program conditions, as seen in Figure 10a, it can be inferred that most of the tunneled carriers during the program pulse are trapped courtesy of the bulk traps in HZO and at HZO/IL interface. Consequently, the span of the memory window for the n-FeFETs gets limited.

The band diagrams under erase/program conditions depicted in Figure 10b for p-channel devices follow a similar approach. The tunneling probabilities for the holes, however, is much lower than that of the electrons and the charge sharing through FN/TAT is effectively minimized. At a sufficiently higher gate bias, there is still a possibility of ‘hot’ hole injection, which may result in the generation of traps at the SiO₂/Si interface. Under the program cycle, similar to the n-channel case, the tunneling of the hole carriers through the SiO₂ is responsible for the shift in the device threshold voltage observed in Figure 5b and Figure 8b. Further, it is also identified that there are multi-level traps present at the HZO/IL interface. These traps are relatively deeper, as discussed in Section 3.1.1, and are responsible for the roll-off in the device V_TH observed during the pulse characterization of the p-FeFET devices in Figure 7c.

4. Discussion

In this work, n-FeFETs and p- FeFET devices have been designed, fabricated and investigated using a similar process flow, which is important for their integration in CMOS circuitry. A systematic and calibrated TCAD study is presented to investigate trapping effects on the asymmetric behavior observed in the transfer and pulse characteristics of n- and p-channel FeFET devices. For model validation, fabricated MFM capacitors are realized, and the P-E hysteresis loops are calibrated against the experimental set. The calibrated deck is then used to model the FeFETs to identify the trapping parameters. The n-FeFETs demonstrate faster complete polarization switching compared to their p-channel counterparts. It has been observed that the fixed charges and interface traps at HZO/IL modulate the subthreshold characteristics of the fabricated FeFETs and are responsible for the asymmetricity observed in the transfer characteristics of the two devices. Further, the IL facilitates the tunneling current due to the presence of traps in the bulk HZO and at HZO/IL. This is responsible for the charge sharing directly between the HZO and the silicon channel and limits the span of the memory window for the fabricated devices. The n-channel devices, as observed, are identified to be more affected compared to p-channel devices, suggesting that electrons are more easily trapped than holes. Further, the characteristic crossover point observed in n-FeFETs was found to be associated with the partial recovery of the polarization dipoles due to the charge trapping mechanism, which results in a temporary switch between ferroelectric based operation to charge based operation.