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0.5-V 281-nW Versatile Mixed-Mode Filter Using Multiple-InPut/Output Differential Difference Transconductance Amplifiers

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03 November 2023

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06 November 2023

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Abstract
This paper presents a new low-voltage versatile mixed-mode filter which uses a multi-ple-input/output differential difference transconductance amplifier (MIMO-DDTA). The multi-ple-input of the DDTA is realized using a multiple-input bulk-driven MOS transistor (MI-BD-MOST) technique to maintain a single differential pair, thereby achieving simple structure with minimal power consumption. In a single topology, the proposed filter can provide five standard filtering functions (low-pass, high-pass, band-pass, band-stop, and all-pass) in four modes: voltage (VM), current (CM), transadmittance (TAM), and transimpedance (TIM). This provides the full capability of a mixed mode filter (i.e., twenty filter functions). Moreover, the VM filter offers high-input and low-output impedances and the CM filter offers high-output impedance; therefore, no buffer circuit is needed. The natural frequency of all filtering functions can be electronically controlled by a setting current. The voltage supply is 0.5 V and for a 4 nA setting current, the power consumption of the filter was 281 nW. The filter is suitable for low-frequency biomedical and sensor applications that require extremely low supply voltages and nano-watt power consumption. For the VM low-pass filter, the dynamic range was 58.23 dB @ 1 % total harmonic distortion. The proposed filter was designed and simulated in the Cadence Virtuoso System Design Platform using the 0.18 µm TSMC CMOS technology.
Keywords: 
Subject: Engineering  -   Electrical and Electronic Engineering

1. Introduction

Active analog blocks, such as the operational amplifier (OA) or the transconductance amplifier (TA), are essential components for electronic devices, communication systems, and sensor interfaces. These blocks typically use the standard two inputs (i.e., a single differential stage). However, it has been confirmed that the use of a block with multiple inputs can reduce the number of components, silicon area, and power dissipation of some applications by a factor of approximately k, where k is the number of TA inputs [1]. Several applications based on this concept have been presented in [1,2,3,4]. Some other examples of multiple-input blocks are the differential difference amplifier (DDA) [5,6,7,8,9], differential difference current conveyor (DDCC) [10,11], differential difference operational floating amplifier (DDOFA) [12], differential difference transconductance amplifier (DDTA) [13,14], and many others. All these blocks allow for more arithmetic operations due to their multiple-input character and are therefore widely used in instrumentation amplifiers, signal conditioning, differential amplification, filters, and many other applications. Although these blocks can reduce an application’s complexity and the number of blocks utilized, their internal structure is more complex than that of a standard two-input block. This is primarily due to the increased number of differential stages that are required to increase the number of inputs. The multiple-input MOS transistor (MI-MOST) provides a solution to avoid this problem and maintain a single differential stage [15,16,17]. It can be used in any standard CMOS technology without constraints. The first experimental results of MI-MOST were presented in [15,16,17] and various applications based on it were presented in [18,19,20,21,22,23,24,25,26,27,28,29].
Filters play an important role in electronic, telecommunication and control systems. They can be used to reduce harmonics and filter noise in an electronic system, to separate or select desired signals, to remove unwanted signals in telecommunication systems, or to reduce the noise component of measurement signals in a control system. There are five common filtering functions that can be classified, namely the low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), band-stop filter (BSF), and all-pass filter (APF). These filtering functions can be designed using passive and active components, called passive filters or active filters, respectively. Second-order filters (or biquad filters) can be used to realize high-order filters applied to a high-fidelity three-ways crossover loudspeaker network and to a phase-locked loop.
Using active device-based filters, second-order LPF, HPF, BPF, BSF and APF (five filter functions) can be provided in a single topology, creating the so-called universal filter. Circuits that can provide voltage-mode (VM) (input and output as voltage), current-mode (CM) (input and output as current), transadmittance-mode (TAM) (input as voltage and output as current) and transimpedance-mode (TIM) (input as current and output as voltage) transfer functions in the same circuit are classified as mixed-mode universal filters. In a perfect mixed-mode universal filter, each mode of the transfer function should provide five filter functions, therefore obtaining twenty filter functions in a single topology. In addition, perfect universal filters should have high input impedance and low output impedance if the input and output are in voltage forms and low input and high output impedance if the input and output are in current forms.
There are many mixed-mode universal filters available in open literature [30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67]. The circuits in [30,31,32,33,34,35,36,37,38,39,40,41,42,43] realize a mixed-mode universal filter using variant active devices such as current conveyors [30,31,32,33,34,35,36,37,38,39], the CFOA (current feedback operational amplifier) [40,41,42], the FTFN (four terminal floating nullor) [43]; however, these filters lack electronic tuning capabilities. The circuits in [44,45,46] use current-controlled current conveyors-based filters to offer electronic tuning capability, but the circuits in [44,45,47] do not provide twenty transfer functions and the circuits in [46,47] require input matching conditions.
To obtain electronic tuning capability, the circuits in [48,49,50,51] use the CCTA (current conveyor transconductance amplifier), the circuit in [52] uses the VDTA (voltage differencing transconductance amplifier), the circuits in [53,54] use the VD-DVCC (voltage differencing differential voltage current conveyor), and the circuits in [55,56] use the VDBA (voltage differencing buffered amplifier). However, the circuits in [48,51,52] do not offer twenty transfer functions, the circuits in [53,54] require active/passive component matching conditions, and the circuits in [55,56] apply input voltage signals via a passive capacitor and/or resistor.
The OTA (operational transconductance amplifier) has been used to realize mixed-mode universal filters [57,58,59,60,61,62,63,64,65,66]. However, the circuits in [57,59,65] require passive or active components, the circuits in [58,61,62,63] do not provide twenty transfer functions, and the circuits in [57,58,64,66] require inverted input signals. It should be noted that the structure of active devices used in [30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66] is not designed for low-voltage low-power filters. Filters for such applications are in high demand especially for biosignals and sensors signal processing. Many filters based on multiple-input DDTA have been presented [67,68,69,70,71,72,73,74].
This paper presents a versatile mixed-mode filter using MIMO-DDTAs. The circuit has six input voltages, three input currents, three output voltages, and two output currents; as such, it offers 61 transfer functions of LPF, BPF, HPF, BSF, and APF in the same topology. The six input voltage terminals possess a high-impedance level, and the three output voltage nodes possess a low-impedance level which is ideal for voltage-mode circuits. The two output current terminals also possess a high-impedance level which can be connected directly to loads without buffer circuit requirements. The natural frequency of the filters can also be controlled electronically. The proposed versatile mixed-mode filter uses a supply voltage of 0.5 V and 281 nW of power consumption.
The paper is organized as follows: Section 2 describes the multiple-input/output DDTA. Section 3 describes the application of the versatile mixed-mode filter and non-ideality analysis. Section 4 presents the simulation results. Finally, the conclusion is given in Section 5.

2. Proposed DDTA Circuit with Multiple-Input and Multiple-Output

The electrical symbol of the proposed multiple-input/output differential-difference transconductance amplifier is shown in Figure 1. Its performance, in an ideal case, is described by Eqn. (1). The circuit possesses one low-impedance output w, which provides a difference of the sums of the voltages Vy+ and Vy-, applied to its non-inverting and inverting terminals, respectively. It further has a high-impedance output o, which provides a current, proportional to the voltage Vw appearing at the w terminal.
V w = V y + 1 + V y + 2 − V y − 1 − V y − 2 I o ± = ± g m V w
The CMOS structure of the proposed circuit is shown in Figure 2. The circuit consists of two blocks, a multiple-input differential-difference amplifier (MI-DDA) and a multiple-output transconductance amplifier (MO-TA).
The MI-DDA can be seen as a two-stage internal OTA, operating in a unity-gain feedback configuration. The first gain stage is formed by the transistors M1-M12, M14, M15, while the second stage is formed by the transistors M13 and M16. The capacitance CC is used for frequency compensation. The first stage can be seen as a current-mirror OTA, with a differential amplifier M1-M10 and a set of current mirrors M5-M12, M6-M11, M14-M15, acting as a differential to single output converter.
The input stage is based on a non-tailed bulk-driven differential pair M1-M4, which behaves as a differential amplifier with high CMRR and PSRR performances, while also being able to operate at extremely low supply voltages [75], even lower than the threshold-voltages of the used MOS transistors. In order to increase the voltage gain, a partial positive feedback (PPF) is applied. The PPF is created by two cross-coupled transistor pairs: M7-M8 and M9-M10. The cross-coupled pairs generate negative conductances that partially compensate the conductances of the diode-connected transistors M2A,B for the “upper” pair, and M5, M6 for the “lower” pair. Therefore, the resulting conductances increase at the drains of these transistors, and consequently, the first stage transconductance and voltage gain also increase. In particular, the upper pair increases the voltage gain from the bulk terminals to the gates of M1A,B [76], while the lower pair increases the current gains of the current mirrors M5-M12 and M6-M11 [77]. The combination of two PPF circuits decreases the overall sensitivity of the transconductance gain of the first stage to transistor mismatch [69]. This achieves a larger voltage gain while maintaining relatively low sensitivity of the input stage and avoiding problems with frequency compensation of the DDA.
In order to realize a differential to difference function without duplicating the input stage, the multiple inputs were realized using the so-called multiple-input BD MOS transistors [15]. The symbol and the implementation of the devices are shown in Figure 3a and Figure 3b, respectively. A passive capacitive voltage divider is applied to the bulk terminal of the MOS transistor, thus creating a multiple-input device. The large resistors RMOSi, used to bias the bulk terminal for DC, are realized using two minimum-size MOS transistors operating in a cut-off region, as shown in Figure 3c.
Assuming 1/ωCBi << RMOSi, the voltage Vb at the bulk terminal of the MI-BD-MOS transistor can be expressed as:
V b = ∑ i = 1 n β i V i
where n is the number of inputs and βi is the voltage gain of the input capacitive divider:
β i = C B i ∑ i = 1 n C B i
Note that with equal CBi, βi =1/n.
The open-loop voltage gain of the DDA can be expressed as:
A v o = β 2 g m b 1 r d s 15 | | r d s 12 g m 16 r d s 16 | | r d s 13 1 − m 1 1 − m 2
where the coefficients m1 and m2 are the ratios of the absolute values of the negative and positive conductances in a lower and upper PPF circuit, respectively [68]:
m 1 = g m 9,10 g m 5,6 + g d s 2 + g d s 3,4 + g d s 7,8 ≅ g m 9,10 g m 5,6
m 2 = g m 7,8 g m 2 + g d s 1 + g d s 5,6 + g d s 9,10 ≅ g m 7,8 g m 2
Note that the above coefficients should always be lower than unity to maintain circuit stability. In the proposed design, m1=m2=0.5. This increased the voltage gain by 12 dB, thus compensating the gain loss introduced by the input capacitive divider (approximately 10 dB) while maintaining the overall circuit sensitivity to transistor mismatch at a relatively low level.
The second block creating the MIMO-DDTA is the multiple output transconductance amplifier. The circuit can be seen as a current-mirror linear OTA. Note that a version of the MI-TA with one positive output was presented and verified experimentally in [18]. Here, a second, inverting output has been added, thus increasing the circuit universality. Transistors M1, M2 and M11, M12 realize an input differential stage. The transistors M11 and M12 operate in a triode region and extend the linear range of the structure. The circuit can be seen as a BD version of the Krummenacher and Joehl transconductor [78], operating in weak inversion. Thanks to the BD approach, the linear range of the circuit is extended η=gm1,2/gmb1,2 times, as compared with its gate-driven (GD) counterpart. In order to obtain optimum linearity, the following condition should be met [18]:
k = W / L 11,12 W / L 1,2 = 0.5
where W and L is the MOS transistor channel width and length, respectively.
Assuming unity current gain of all current mirrors, the circuit transconductance is given by:
g m = η 4 k 4 k + 1 · I s e t n p U T
where np is the subthreshold slope factor, UT is the thermal potential and Iset is the biasing current. Note that the circuit transconductance is proportional to this current.
In order to increase the DC voltage gain of the structure while not limiting its output voltage range, all current mirrors are based on self-cascode transistors. Consequently, the DC voltage gain from the input to the differential output is equal to:
A V O ≅ 2 g m [ g m 9 r d s 9 r d s 9 c | | g m 6 r d s 6 r d s 6 c ]
Thanks to the self-cascode technique, it is possible to compensate for the gain loss associated with the application of the BD technique. In practice, a voltage gain of around 40 dB can be obtained.

3. Versatile Mixed-Mode Filter

Figure 4 shows the proposed versatile mixed-mode universal filter employing four MIMO-DDTAs and two grounded capacitors. Using (1) and nodal analysis, the output voltages Vo1, Vo2, Vo3 and the output currents Io1, Io2 can be given by:
V o 1 = g m 3 g m 4 · s 2 C 1 C 2 V 5 − V 6 + s C 1 g m 2 V 3 − V 4 + g m 1 g m 2 V 1 − V 2 s 2 C 1 C 2 + s C 1 g m 3 + g m 2 g m 3
V o 2 = s 2 C 1 C 2 V 5 − V 6 + s C 1 g m 2 V 3 − V 4 + g m 1 g m 2 V 1 − V 2 s 2 C 1 C 2 + s C 1 g m 3 + g m 2 g m 3
V o 3 = s C 2 g m 3 V 5 − V 6 + s 2 C 1 C 2 + s C 2 g m 3 V 3 − V 4 + s C 2 g m 3 + g m 1 g m 3 V 1 − V 2 s 2 C 1 C 2 + s C 1 g m 3 + g m 2 g m 3
I o 1 = g m 3 · s 2 C 1 C 2 V 5 − V 6 + s C 1 g m 2 V 3 − V 4 + g m 1 g m 2 V 1 − V 2 s 2 C 1 C 2 + s C 1 g m 3 + g m 2 g m 3
I o 1 = − s 2 C 1 C 2 I 3 + s C 1 g m 3 I 2 − g m 2 g m 3 I 1 s 2 C 1 C 2 + s C 1 g m 3 + g m 2 g m 3
I o 2 = s 2 C 1 C 2 I 3 − s C 1 g m 3 I 2 + g m 2 g m 3 I 1 s 2 C 1 C 2 + s C 1 g m 3 + g m 2 g m 3
V o 1 = 1 g m 4 · − s 2 C 1 C 2 I 3 + s C 1 g m 3 I 2 − g m 2 g m 3 I 1 s 2 C 1 C 2 + s C 1 g m 3 + g m 2 g m 3
From (10)-(16), the variant filtering functions can be determined and are shown in Table 1. The proposed mixed-mode universal filter can offer LP, HP, BP, BS, and AP filtering functions of VM, CM, TAM, and TIM in the same topology. Thanks to the multiple inputs of the DDTA, the VM, CM, and TIM can offer non-inverting and inverting transfer functions of LP, HP, BP, BS, and AP filters, and the VM and TAM can also offer differential transfer functions of LP, HP, BP, BS, and AP filters. Thus, the proposed mixed-mode filter can provide 61 transfer functions in a single topology. Thanks to the multiple outputs of the DDTA, such as DDTA4, the proposed filter utilizes a minimum number of used DDTAs while offering inverting and non-inverting transfer functions of LP, HP, BP, BS, and AP filters of CM. The input signals V1 to V6 are connected to the high-impedance terminals of the DDTA; thus, the voltage signals can be applied without any buffer circuit requirements. The output signals Vo1 to Vo3 are connected to the low-impedance terminals of the DDTA, which offers a cascadable output for the voltage-mode filter structures. The output signals Io1 and Io2 are connected to the high-impedance terminals of the DDTA, which offers a cascadable output for the current-mode filter structures. However, in the case of CM, the inputs I1 to I3 require additional circuits, such as multiple-output current followers or multiple-output current mirrors, to create three identical current signals from the single original current signal. It is clear that the proposed filter is exempt from inverting-type input signal and input matching conditions for realizing all filtering functions both in the case of voltage and current signals.
The voltage gain gm3⁄gm4 of the filtering functions can be obtained if the output Vo1 is used. In the case of TAM, the inputs V1 to V6 are converted to output currents by gm3; in the case of TIM, the input currents I1 to I3 are converted to output voltages by gm4.
The natural frequency (ωo) and the quality factor (Q) can be given by:
ω o = g m 2 g m 3 C 1 C 2
Q = C 2 g m 2 C 1 g m 3
It should be noted that the parameter ωo can be controlled electronically by gm2 and gm3 and the parameter Q can be given by C2/C1.

3.1. Non-Ideality Analysis

Taking the tracking errors and the non-ideal transconductance of the MIMO-DDTA into account, the characteristics of the MIMO-DDTA can be rewritten as:
V w = α j + V y + 1 + α j + V y + 2 − α j − V y − + α j − V y − 2 I o = g m n j V w
where αj+=1-εj+v and εj+v (|εj+v |≪1) denote the voltage tracking error from non-inverting terminals (i.e., Vy+1, Vy+2) to the w-terminal (i.e., Vw) of the j-th DDTA, αj-=1-εj-v and εj-v (|εj-v |≪1) denote the voltage tracking error from inverting terminals (i.e., Vy-1, Vy-2) to the w-terminal (i.e., Vw) of the j-th DDTA, and gmnj is the non-ideal transconductance gain of the j-th DDTA. The non-ideal transconductance gmnj of the j-th DDTA at a frequency near the cut-off frequency can be expressed by [65]:
g m n j s ≅ g m j 1 − μ j s
where μj=1⁄ωgmj , ωgmj denotes the first pole frequency of the j-th gm.
Using (19), the denominator of (10)-(16) can be modified as:
s 2 C 1 C 2 + s C 1 g m n 3 α 3 − + g m n 2 g m n 3 α 2 + α 3 −
Using (20), (21) becomes:
s 2 C 1 C 2 1 − C 1 g m 3 μ 3 α 3 − − g m 2 g m 3 α 2 + α 3 − μ 2 μ 3 C 1 C 2 + s C 1 g m 3 α 3 − 1 − g m 2 g m 3 α 2 + α 3 − μ 2 + μ 3 C 1 g m 3 α 3 − + g m 2 g m 3 α 2 + α 3 −
The tracking errors and the non-ideal effect of the transconductance of the DDTA can be made negligible by satisfying the following condition:
g m 2 g m 3 α 2 + α 3 − μ 2 + μ 3 C 1 g m 3 α 3 − ≪ 1 C 1 g m 3 μ 3 α 3 − − g m 2 g m 3 α 2 + α 3 − μ 2 μ 3 C 1 C 2 ≪ 1
The modified natural frequency (ωon) and the modified quality factor (Qn) can be expressed as:
ω o n = g m 2 g m 3 C 1 C 2 · α 2 + α 3 −
Q n = C 2 g m 2 C 1 g m 3 · α 2 + α 3 −
To consider the parasitic impedances that affect the proposed mixed-mode filter, the parasitic capacitance Co and parasitic conductance go (go=1/Ro, Ro is the output resistance) at the o-terminal of the DDTA are considered while the parasitic impedances at the y- and w-terminals are neglected. Considering Figure 4, the parasitic capacitances Co1, Co4 and parasitic conductances go1, go4 are parallel with C1 and the parasitic capacitances Co2, Co4, and parasitic conductances go2, go4 are parallel with C2. Co1, Co2, Co4 are respectively the parasitic capacitances at the o-terminal of DDTA1, DDTA2, DDTA4, and go1, go2, go4 are respectively the parasitic conductances at the o-terminal of DDTA1, DDTA2, DDTA4. The parasitic capacitances can be neglected by appropriately choosing values such that C1 ≫ Co4 + Co4, C2 ≫ Co2 + Co4, gm2≫go1+go4, and gm3≫go2+go4.

4. Simulation Results

The circuit was designed and simulated using the Cadence Virtuoso System Design Platform using 0.18µm CMOS technology from TSMC. The voltage supply was ±250mV (0.5V) and the bias voltage VB1=-100mV. The transistor aspect ratios are included in Table 2.
For the filter application, the value of capacitors C1=C2=20pF was chosen. The frequency responses of the gain and phase for the differential input VM, non-inverting CM, TAM and TIM filter with Iset1-4=4nA are shown in Figure 5. The cutoff frequency was 211 Hz, and the power consumption was 281nW.
The frequency responses of LP, HP, BP, BS, and AP gains and phases for VM are shown in Figure 6. The wide tunability of the filter is achieved by varying the setting current Iset1-4=(0.5, 1, 2, 4)nA, where the cutoff frequency was (28, 56, 112, 211)Hz, respectively.
Monte Carlo (MC) analysis was used to perform the statistical analysis to estimate the parametric yield and generate information about the performance characteristics of the differential input VM filter. The gains frequency responses of LP, HP, BP, BS, AP with 200 runs MC are shown in Figure 7. The curves are overlapping or close to each other.
The process, voltage, temperature (PVT) corners were also used to confirm the robustness of the design. The process transistor corners were: fast-fast, fast-slow, slow-fast, slow-slow. The process MIM capacitor corners were: fast-fast and slow-slow. The voltage supply corners were =±10% (VDD-VSS) and the temperature corners were -20°C and 70°C. The results for the gains frequency responses of LP, HP, BP, BS, AP with PVT are shown in Figure 8. The curves are again overlapping or close to each other, which confirms the robustness of the filter design. Any frequency deviation can be easily adjusted by the setting current.
The transient response of the VM LPF with an applied input sinusoidal signal Vin-pp=200mV@10Hz is shown in Figure 9 (a). The spectrum of the output signal is shown in Figure 9 (b), where the total harmonic distortion (THD) of 0.23% is indicated.
The THD for the VM LPF with different peak-to-peak input signal values @ 10Hz is shown in Figure 10. The 1% THD is achieved for Vin-pp=300mV. The output voltage noise for the VM LPF is shown in Figure 11. The root-mean square (RMS) output noise integrated in the bandwidth of 1 to 211 Hz was 130 μV; thus, the dynamic range (DR) of the VM LPF filter is 58.23dB @ 1% THD.
The proposed versatile mixed-mode filter was compared with the previously reported filters in [34,37,55,56,65,66,67] as shown in Table 3. Compared with these previous works, the proposed filter offers the most transfer functions of the five standard filtering functions and the lowest voltage supply. Compared with [34,35], the proposed filter offers electronic tuning capability of the natural frequency; compared with [65,66,67], the proposed filter uses fewer active devices. The filters in [37,55,56] apply the input signal via capacitor and/or resistor, the structure in [55] does not provide five standard filtering functions of VM, CM, TAM, and TIM, and the filters in [55,56] require input matching conditions for realizing some filtering functions.

5. Conclusions

This paper presents a 0.5-V, 281 nW versatile mixed-mode universal filter using MIMO-DDTAs. The MIMO-DDTA is used to realize a versatile mixed-mode universal filter that offers many transfer functions in the same topology. For the VM LP filter, the dynamic range was 58.23dB @ 1% total harmonic distortion. The proposed filter was designed and simulated in the Cadence Virtuoso System Design Platform using the 0.18µm CMOS technology from TSMC. The simulation results, including Monte-Carlo and PVT corners, confirm the functionality of the design.

Author Contributions

Conceptualization, F. Khateb, M. Kumngern, and T. Kulej; methodology, M. Kumngern and F. Khateb; software, F. Khateb; validation, F. Khateb and T. Kulej; formal analysis, T. Kulej, M. Kumngern, F. Khateb, investigation, F. Khateb and M. Kumngern; resources, F. Khateb, and M. Kumngern; writing—original draft preparation, M. Kumngern, F. Khateb and, T. Kulej; writing—review and editing, F. Khateb, T. Kulej; visualization, F. Khateb, T. Kulej and M. Kumngern; supervision, F. Khateb; project administration, F. Khateb; funding acquisition, F. Khateb and M. Kumngern. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the University of Defence within the Organization Development Project VAROPS.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Electrical symbol of the MIMO-DDTA.
Figure 1. Electrical symbol of the MIMO-DDTA.
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Figure 2. CMOS structure of the MIMO-DDTA.
Figure 2. CMOS structure of the MIMO-DDTA.
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Figure 3. MI-BD MOST: (a) symbol, (b) possible implementation, (c) implementation of RMOS.
Figure 3. MI-BD MOST: (a) symbol, (b) possible implementation, (c) implementation of RMOS.
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Figure 4. The proposed versatile mixed-mode filter using MIMO-DDTAs.
Figure 4. The proposed versatile mixed-mode filter using MIMO-DDTAs.
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Figure 5. The frequency characteristics of gains for the VM (a), CM (b), TAM (c), and TIM (d).
Figure 5. The frequency characteristics of gains for the VM (a), CM (b), TAM (c), and TIM (d).
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Figure 6. The frequency characteristics of gains (lines) and phases (points) for the VM filter: LPF (a), HPF (b), BPF (c), BSF (d), and APF (e).
Figure 6. The frequency characteristics of gains (lines) and phases (points) for the VM filter: LPF (a), HPF (b), BPF (c), BSF (d), and APF (e).
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Figure 7. The 200 runs MC frequency characteristics of the gains for the differential input VM filter: LPF (a), HPF (b), BPF (c), BSF (d), and APF (e).
Figure 7. The 200 runs MC frequency characteristics of the gains for the differential input VM filter: LPF (a), HPF (b), BPF (c), BSF (d), and APF (e).
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Figure 8. The PVT frequency characteristics of the gains for the VM filter: LPF (a), HPF (b), BPF (c), BSF (d), and APF (e).
Figure 8. The PVT frequency characteristics of the gains for the VM filter: LPF (a), HPF (b), BPF (c), BSF (d), and APF (e).
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Figure 9. The transient response of the VM LPF (a) and the spectrum of the output signal (b).
Figure 9. The transient response of the VM LPF (a) and the spectrum of the output signal (b).
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Figure 10. The THD of the VM LPF with different peak-to-peak input voltages @ 10Hz.
Figure 10. The THD of the VM LPF with different peak-to-peak input voltages @ 10Hz.
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Figure 11. The output voltage noise of the VM LPF.
Figure 11. The output voltage noise of the VM LPF.
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Table 1. Obtaining variant filtering functions of the proposed versatile mixed-mode filter.
Table 1. Obtaining variant filtering functions of the proposed versatile mixed-mode filter.
Operation mode Filtering Function Input Output
VM LP Non-inverting V 1 V o 1
Inverting V 2 V o 1
Non-inverting V 1 V o 2
Inverting V 2 V o 2
Non-inverting V 1 = V 6 V o 3
Inverting V 2 = V 5 V o 3
Differential V 1 − V 2 V o 2
BP Non-inverting V 3 V o 1
Inverting V 4 V o 1
Non-inverting V 3 V o 2
Inverting V 4 V o 2
Non-inverting V 5 V o 3
Inverting V 6 V o 3
Differential V 3 − V 4 V o 2
HP Non-inverting V 5 V o 1
Inverting V 6 V o 1
Non-inverting V 5 V o 2
Inverting V 6 V o 2
Non-inverting V 3 = V 6 V o 3
Inverting V 4 = V 5 V o 3
Differential V 5 − V 6 V o 2
BS Non-inverting V 1 = V 5 V o 1
Inverting V 2 = V 6 V o 1
Non-inverting V 1 = V 5 V o 2
Inverting V 2 = V 6 V o 2
Differential V 1 = V 5 − V 2 = V 6 V o 2
AP Non-inverting V 1 = V 4 = V 5 V o 1
Inverting V 2 = V 3 = V 6 V o 1
Non-inverting V 1 = V 4 = V 5 V o 2
Inverting V 2 = V 3 = V 6 V o 2
Differential V 1 = V 4 = V 5 − V 2 = V 3 = V 6 V o 2
CM LP Non-inverting I 1 I o 1
Inverting I 1 I o 2
BP Non-inverting I 2 I o 2
Inverting I 2 I o 1
HP Non-inverting I 3 I o 1
Inverting I 3 I o 2
BS Non-inverting I 1 = I 3 I o 1
Inverting I 1 = I 3 I o 2
AP Non-inverting I 1 = I 2 = I 3 I o 1
Inverting I 1 = I 2 = I 3 I o 2
TAM LP Non-inverting V 1 I o 1
Inverting V 2 I o 1
Differential V 1 − V 2 I o 1
BP Non-inverting V 3 I o 1
Inverting V 4 I o 1
Differential V 3 − V 4 I o 1
HP Non-inverting V 5 I o 1
Inverting V 6 I o 1
Differential V 5 − V 6 I o 1
BS Non-inverting V 1 = V 5 I o 1
Inverting V 2 = V 6 I o 1
Differential ( V 1 = V 5 ) − ( V 2 = V 6 ) I o 1
AP Non-inverting V 1 = V 4 = V 5 I o 1
Inverting V 2 = V 3 = V 6 I o 1
Differential V 1 = V 4 = V 5 − V 2 = V 3 = V 6 I o 1
TIM LP Non-inverting I 1 V o 1
BP Inverting I 2 V o 1
HP Non-inverting I 3 V o 1
BS Non-inverting I 1 = I 3 V o 1
AP Non-inverting I 1 = I 2 = I 3 V o 1
Table 2. Transistor aspect ratios of the MIMO-DDTA.
Table 2. Transistor aspect ratios of the MIMO-DDTA.
MI-DDA W/L (µm/ µm)
M1A, M2A, M1B, M2B M14, M15 16/3
M3-M8, M11-M12, MB 8/3
M9, M10 4/3
M16 6×16/3
M13 6×8/3
MR 4/5
MIM capacitor: CB= 0.5 pF, Cc= 6 pF
MO-TA W/L (µm/ µm)
M1, M2 2×15/1
M3-M6, M14-M16 2×10/1
M3c-M6c, M14c-M16c 10/1
M7-M10, M17-M19, M13 2×15/1
M7c-M10c, M17c-M19c, M13c, M11, M12 15/1
Table 3. Comparison of the proposed filter’s properties with those of mixed-mode universal filters.
Table 3. Comparison of the proposed filter’s properties with those of mixed-mode universal filters.
Factor Proposed [34] [37] [55] [56] [65] [66] [67]
Number of active devices 4-DDTA 3-DDCC 1-FDCCII, 1-DDCC 2-VDBA 3-VDBA 5-OTA 8-OTA 5-DDTA
Realization 0.18 µm CMOS 0.25 µm CMOS 0.18 µm CMOS 0.18 µm CMOS 0.18 µm CMOS 0.18 µm CMOS 0.18 µm CMOS 0.18 µm CMOS
Number of passive devices 2-C 2-C, 3-R 2-C, 6-R 2-C, 2-R 2-C, 1-R 2-C 2-C 2-C
Type of filter MIMO MISO MIMO MIMO MIMO MISO MIMO MIMO
Total number of offered responses 61 30 36 17 20 20 20 36
Each mode offers five standard responses Yes Yes Yes No Yes Yes Yes Yes
Orthogonal control of ω o and Q Yes Yes Yes Yes Yes Yes Yes Yes
Electronic control of ω o Yes No No Yes Yes Yes Yes Yes
All passive devices grounded Yes Yes No No No Yes Yes Yes
High input impedances for VM Yes Yes No No No Yes Yes Yes
No need for input matching conditions Yes Yes Yes Yes No Yes Yes Yes
No need for inverting input conditions Yes Yes Yes Yes Yes Yes Yes Yes
Power supply (V) 0.5 ±1.25 ±0.9 ±0.75 ±1.25 ±0.9 ±0.3 1.2
Power dissipation (mW) 0.281×10-3 - - 0.373 5.482 0.1773 0.00577 0.33
Natural frequency (kHz) 0.211 3.315×103 1.591×103 1.44×103 16.32×103 3.39×103 5 1.04
Total harmonic distortion (%) 1@300mVpp (LPF) 0.723@60µApp 2.2@300mVpp 2.2@200mVpp <4@350mVpp (HPF) - 2@120mVpp (LPF) 1.09@650mVpp
Dynamic range (dB) 58.23 - - - - - 53.2 -
Verification of result Sim Sim Sim Sim/Exp Sim/Exp Sim Sim Sim/Exp
Note: MIMO=multiple-input multiple-output, MISO=multiple-input single-output
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Copyright: This open access article is published under a Creative Commons CC BY 4.0 license, which permit the free download, distribution, and reuse, provided that the author and preprint are cited in any reuse.
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