Preprint Review Version 1 Preserved in Portico This version is not peer-reviewed

Performance Scaling of Silicon after Moore’s Law

Version 1 : Received: 29 November 2023 / Approved: 30 November 2023 / Online: 30 November 2023 (10:33:35 CET)

How to cite: Venkatachalam, O. R. Performance Scaling of Silicon after Moore’s Law. Preprints 2023, 2023111929. https://doi.org/10.20944/preprints202311.1929.v1 Venkatachalam, O. R. Performance Scaling of Silicon after Moore’s Law. Preprints 2023, 2023111929. https://doi.org/10.20944/preprints202311.1929.v1

Abstract

Semiconductors play a very important role in modern society. The improvement in performance of semiconductors is what has enabled the world to grow at such a fast pace. For decades scaling has been done through Moore’s law i.e performance improvements have been obtained due to transistor scaling where the number of transistors per unit area increase is what has contributed to the increase in performance. However, with transistor scaling reaching its limitations we need to find alternate methods to enhance silicon design to suit the computational need of modern society. To address this problem we will be looking into a few methods that enable performance scaling with a focus on analysing the most popular implementation of each in the industry.

Keywords

semiconductors; chips; hardware; large scale silicon die; chiplets; quantum hardware

Subject

Engineering, Electrical and Electronic Engineering

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