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State-Space Modelling and Stability Analysis of Solid-State Transformers for Resilient Distribution Systems

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27 December 2023

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28 December 2023

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Abstract
Solid-state transformer (SST) is a promising technology for smart grids due to its flexible power control (better reliability) and high efficacy (by decreasing losses) compared with traditional transformers. The SST is designed in tandem with three stages, i.e., the input, isolation, and output stages. As three converter stages are used to design the SST to make a more reliable device in practice, it is highly prone to instabilities. Moreover, the key objective of SST design is to implement a modern power distribution system to make it more intelligent and reliable. The stability issue can be even more complicated by the presence of distributed energy resources in the distribution system. Thus, the stability of SST must be measured prior to /during the design, and to determine, a state-space model is used, which is developed in this paper. Each stage of SST is modeled with its controller, and the system's stability is measured through the controllability and observability test. Further, the conversion from state-space to transfer function model is done, and the stability of SST is shown using frequency and time-domain diagrams. With these, the different plots, namely, the Bode plot, Nyquist plot, Nichols chart, Root locus, pole-zero plot, and Eigen plot, are used to ascertain the relative and absolute stability. Finally, the SST Simulink model is tested and validated through hardwate-in-the-loop simulation, i.e., OPALRT, to show its effectiveness and applicability.
Keywords: 
Subject: Engineering  -   Electrical and Electronic Engineering

1. Introduction

Over the past few decades, extreme events such as natural disasters, cyber-attacks, power system equipment failures, and power thefts have increased, eventually impacting the power system infrastructure, including distribution systems [1]. Consequently, a power system blackout may occur, affecting people's social and economic life [2]. As traditional power system networks are large ring systems, an extreme event may affect many loads and components [3]. However, much research has been carried out in the area of power system migration, where the main aim was to convert from bulk power networks to small-scale networks [4,5]. The small-scale networks have been established through the development of renewable energies (RESs) and their integration into bulk power networks [6], for example, microgrids (MGs) and smart grids (SGs). These are generally connected to the bulk power system, making them a grid-connected mode [7,8]. Further, it can change to the islanded mode while in events to avoid corresponding impacts on the distribution system and supply the local loads [9]. Furthermore, the deployment of MGs and SGs can enhance system reliability and resiliency of the power distribution system in responding to extreme operating conditions.
As noted, it has been seen that the integration of RESs has increased during the past few decades, which plays a crucial role in the distribution systems for grid modernization [10]. However, due to the intermittency of the RESs, it has certain challenges, which make the system complex and unstable. The most noticeable challenge is uncertainty, which means it depends on environmental factors such as solar insolation and wind speed for solar and wind systems, respectively [11]. To deal with these challenges, the advanced power electronics in distribution systems play a crucial role in regard to the control of power (both active and reactive power) flow to enable DC-operated technology[12], protection [13], mitigating the power quality issues, and reducing harmonics. To address these benefits, power electronics are reconfigured in a different way to make it possible for the determination of power quality problems [14]. It is critical for the distribution networks that the reliability factor is always a prime concern—with this objective, using a modern power electronics device, a solid-state device is pronounced, named as the SST. SST is treated as an evolving technology for providing power supply to the consumer through MGs or SGs [15]. Besides, the SST is a high-frequency transformer with a power electronic converter and is an alternative to the traditional bulky and non-smart transformer.
In the past decades, researchers have shown interest in modeling and the development of SST for MG and SG applications. In [16,17], the design and response of SSTs are addressed through their converter stages and controllers. In [18], average models and their controllers are proposed and explored through descriptive simulation studies. Further, in [19], the stability aspect of SST and validation, which has been done through the distribution system, is presented. In this regard, many motivating test models of transient instabilities have been developed, and their importance to the link topologies of SSTs in various operating regions is demonstrated [20]. The most prominent manufacturers of SST, namely, ABB, ETH Zurich, EPRI, Siemens, and FREEDM Systems Center, have conducted cutting-edge research to upgrade the conventional transformer to an intelligent one. They have designed and tested various topologies to improve the performance and facilities of SST to the connected devices [21,22,23,24,25,26]. In [26], the FREEDM Systems Center is presented with a start-up SST structure named Generation-1-SST, which can be used in medium-voltage-based MG. Further development has been done with a multi-cell-based DC-DC converter for SST, which is proposed in [27]. However, the research on SST stability is lacking in the literature and must be considered a vital factor. Thus, the stability aspect of each stage (input, isolation, and output) of the SST needs to be emphasized, which this paper addresses. The main contribution of this work is detailed as follows.
This study develops a state-space and a transfer-function-based model with a proper SST controller to reduce system complexity and cost. The state-space parameters (A, B, C, and D) of the converter's input, insolation, and output stages are estimated. Each converter stage has its own controller and filter circuit. The PI controller is implemented in this design due to its simplicity, robustness, and excellent control action. The transfer function model of each converter is derived from the state-space model. By using the transfer function equation, the stability of the proposed design is tested in terms of frequency response, time response, controllability, and observability. Furthermore, the Simulink design of the proposed system is established in Matlab software, and the controller is designed through MATLAB SISOTOOL. The state-space model is designed for the stability study with and without a controller. In the proposed methodology, the user can simply design the controller part from the unstable model through MATLAB SISOTOOL, thereby making the system robust and stable. Thus, researchers can easily measure the system's stability, sensitivity, controllability, and observability.
This article is organized as follows. Section 1 provides an introduction to SST and a literature review. Section 2 outlines the fundamentals and different types of SST topology. In Section 3, the continuous-time average state-space model and its transfer function model are formulated. In this section, the converter stage is categorized into the input, isolation, and output stages. Then, each stage's state, model, and control parameters are derived. Finally, the result and discussion parts of the proposed model are provided in Section 4, followed by the conclusions in Section 5.

2. Fundamental topologies of SST

Various architectures are available for each of the three stages of SST. The topology is determined depending on the application of SST. The different types of topologies are Type-A (A-1 and A-2), Type-B, Type-C, Type-D, and Type-E [28]. This study adopts the Type-D-based SST topology [32] because it has numerous advantages, such as DC connectivity, fault isolation, proper voltage regulation, easy integration with RESs and storage, and volt-ampere reactive (VAR) compensation. In the design, the architecture for each stage should be chosen appropriately, and the problems should be addressed by integrating them into a single system to deliver regulated voltage at each stage.
The fundamental three-stage architecture of SST is presented in Figure 1. The input stage, which is also called the AC–DC stage, contains a single-phase AC–DC IGBT-based converter that operates at a high switching frequency. The isolation stage, which is also called the DC-DC stage, comprises two H-bridges with a high-frequency transformer. A DAB converter is also applied in this stage [29]. The output of the input stage is fed to the DAB converter, and the output of the converter is fed to the inverter or is considered the output stage. In the output stage, a filter circuit is added to mitigate the voltage and power quality issues. The output stage is usually supplied to low-voltage user applications.

3. Continuous-time average state-space model

In this section, the design of the state-space model and the continuous-time transfer function model is formulated. The controller of each stage is derived to enhance system stability and performance. Furthermore, the different parameters are calculated and presented in tables to determine the stability, frequency level range, and DC gain of each stage.

3.1. Input stage (AC-DC)

Formulation: The input stage of the SST is the conversion of AC to DC signal, shown as architecture and equivalent diagram in Figure 2. (a) and Figure 2. (b), respectively. Eq. (1) and Eq. (2) represent the input voltage; however, in Eq. (2), the duty cycle is taken as an average over a switching time. Referred to Figure 2. (b), Eq. (3) is formed by applying the KVL equation. Further, considering changes as a minute value in the DC signal, Eq. (3) can be modified as Eq. (4). Eq. (5) is solved by having Eq. (3) and Eq. (4). Thereafter, by applying Laplace transform to Eq. (5), Eq. (6) and its updated version in Eq. (7) are obtained, which represent the open-loop transfer function of the input stage with the inductor current.
Further, the transfer function of the input stage through DC-link capacitance current is presented in Eq. (8). Similarly, Eq. (9)-(11) is solved to reach Eq. (12), which represents the ratio of the change in output DC link voltage to any change in input current.
U s ( t ) = U dc   D =   K m sin ( ω t )   U dc
U s ( t ) = U dc   D 1 ( t ) = U m sin ( ω t )
U m sin ( ω t ) U dc   D 1 ( t )   = L f   d ( i ls ( t ) ) dt
U mdc sin ( ω t ) U dc ( D 1 + D 1 ) ( t ) = L f d ( i ls + i ls ( t ) ) dt
D 1 ( t ) U dc = L f d   i ls dt
D 1 ( s ) U dc = sL s i ls ( s )
i ls ( s ) D 1 ( s ) = U dc sL s = G in      
C f dU dc ( t ) dt = D 1 ( i ls ( t ) )
C f d ( U dc ( t ) + U dc ( t ) ) dt = D 1 ( ( i ls ( t ) + i ls ( t ) ) )
C f d ( U dc ( t ) ) dt = 1 C f   D 1 ( i ls ( t ) )
s U dc ( s ) = 1 C f   D 1 ( i ls ( t ) )
U dc ( s ) i ls ( t ) = D 1 s C f = G vi
State Space Model: Furthermore, the state-space model presented in Eq. (13) and (14) denotes the state and output equation of the system where A, B, C, and D are the state, control, output, and transmission matrices, respectively. The overall transfer function of the input stage has been derived, and the state space parameters are measured in the results section [30]. Here x is the state variable, which are: inductor current ( i ls ) and capacitor voltage ( U dc ) and u is the input as U ref .
x · = A x + B u
y = C x + D u
Considering the input stage transfer function as derived in (7) and (12), two controllers have been designed using MATLAB SISOTOOL. Thus, corresponding to G vi and G in , the PI controllers are g P I 1 and g P I 2 , respectively.
g P I 1 = 3.82 × 10 6 + 6.5 × 10 6 s
g P I 2 = 2.7 × 10 6 + 259.2 × 10 6 s

3.2. Isolation stage (DC-DC)

In this stage, the DAB converter is considered for DC-DC conversion. A high-frequency transformer is placed between DAB, as depicted in Figure 4. (a), and the equivalent diagram is depicted in Figure 4. (b). The DAB converter deals with three main parameters, namely, phase shift between two bridges (Ø), duty cycle ratios (D), and switching frequency (fs). The other parameters are as follows: R tf represents the equivalent of winding resistance and switching on resistance; L tf is the leakage inductance of the proposed transformer referred to as the secondary side; T 1 , T 2 , T 3 , T 4 , T 4 , T 5 , and T 6 are the converter switches; and U 1 , and U 2 are the primary and secondary winding voltages, respectively. The leakage inductance is calculated using Eq. (20). Refer to Eq. (15), the variation in transformer output with different frequencies and leakage inductance is shown in Figure 5.
Moreover, the duty cycle ratio of the proposed scheme is fixed to 0.5. Subsequently, the phase shift modulation technique is used here to control the operation of DAB. The transferred power from one stage of DAB to the other stage can be expressed in Eq. (16). Further, the state-space model of the DAB can be formulated as Eq. (17) by assuming the two-state variables of the proposed systems, namely, the current through the inductor ( i L ) and the voltage across the capacitor ( U 0 ). Eqs. (17) and (18) are time-variant and nonlinear. To ensure that the system is time-invariant and linear, the traditional state-space averaging procedure is applied to characterize a state variable x(t) by utilizing its Fourier series expansion as given in Eq. (19). When the Fourier analysis is applied in Eqs. (17) and (18), Eq. (20)-(25) are obtained. In this Fourier analysis, only the 0th and 1th order terms are considered, while other higher-order terms of state variables are neglected.
  P = U 2 2 × π × f × L ( 1 π )
  P DAB = U dc U 0 2 Nf s L tf D ( 1 D )
here, L tf = L 1 N 2 + L 2
    di L ( t ) dt = R tf L tf i L ( t ) + T 1 ( t ) L tf U dc ( t ) T 3 ( t ) L tf U 0 ( t )
    dU ( t ) dt = 1 RC 0 U ( t ) + T 2 ( t ) C 0 i L ( t ) I 0 C 0
  X ( t ) = k = X k ( t ) e jk ω t
where ω =2πf and Xk(t) is the kth coefficient in the Fourier series analysis.
d   U o 0   dt = d   i o 0   C 0 U o 0   RC 0 + T 2 0   C 0 i L o + 2 T 2 1 real   C 0 i L 1 real + 2 T 2 1 imag   C 0 i L 1 imag
d   U o 1 real   dt = i o 1 real   C 0 U o 1 real   RC 0 ω U o 1 imag + T 2 0   C 0 i L 1 real + T 2 1 real   C 0 i L 0
d   U o 1 imag   dt = i o 1 imag   C 0 U o 1 imag   RC 0 ω U o 1 real + T 2 0   C 0 i L 1 imag + T 2 1 imag   C 0 i L 0
d   i L 0   dt = R tf   L tf i L 0 + 1 L tf U dc 0 T 1 0 + 2 T 1 real   L tf U dc 1 real + 2 T 1 1 imag   L tf U dc 1 imag 1 L tf U oc 0 T 2 0 + 2 T 2 real   L tf U o 1 real + 2 T 2 1 imag   L tf U o 1 imag
d   i L 1 real   dt = R tf   L tf i L real +   ω i L 1 imag + U dc real   L tf T 1 0 + T 1 1 real U dc 0 T 2 0   L tf U o 1 real + T 2 1 real U o 0
          d   i L 1 imag   dt = R tf   L tf i L imag +   ω i L 1 real + U dc imag   L tf T 1 0 + T 1 1 imag U dc 0 T 2 0   L tf U o 1 imag + T 2 1 imag U o 0
The transient behavior of the DAB converter in terms of voltage variations is considerably slower in the input than in the output. Therefore, the 0th term of input voltage is U d c 0 = U dc and i o 0 = i 0 . The transient behavior of the first term of input voltage and load current is neglected, which are U 1 real and i 1 real . In this design, the converters are operating in 50% of the duty cycle. Thus, the first-order terms of T 1 (t) and T 2 (t) are similar to zero order and are presented in Eqs. (26)-(29). Moreover, in Eqs. (17) and (18), the independent state variables are the inductor current and capacitor voltage, which form the state-space model of the DAB converter with the state vector x(t) and the control vector u(t). Further, Eqs. (30) and (31) represent the state-space model with the input and output signals of the DAB converter. Therefore, the model parameters are input voltage source ( U dc   ), inductor current ( i L ), and duty cycle (D). When T 1 1 i m a g and T 1 1 r e a l are introduced into Eqs. (20), and (25), the state-space model becomes Eq. (31). Furthermore, the zero initial states are assumed in Eq. (32), which are, i L 0 , U o 1 real , U o 1 imag are similar to zero order, and Eq. (32) becomes Eq. (33).
T 1 1 i m a g = 2 π
T 1 1 r e a l = 0
T 2 1 i m a g = 2 cos D π π
T 2 1 r e a l = 2 sin D π π
X ( t ) dt = A 1 x ( t ) + B 1 u ( t )
Y ( t ) = C 1 x ( t ) + D 1 u ( t )
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A small signal control for the output transfer function is needed to measure the system stability of the DAB converter with the controller structure. Thus, a small deviation in D causes a distinction in the values of U o 0 from its steady-state value. Hence, the corresponding small signal model is defined in Eqs. (34)-(37). In addition, the nonlinearity of the system is introduced when the control and state variables are multiplied. The approximation solution of nonlinear terms is presented in Eq. (38). To this end, given the value of parameters defined in Eqs. (34)-(37) are placed into Eq. (33), then the state-space model can be expressed as in Eq. (39) while the corresponding values are given in A, B, C, and D matrix form. Further, the transfer function of the DAB converter can be expressed using a conversion formula, which is given in Eq. (40), and the values are assigned and given in Eq. (41), where G open loop is the open-loop transfer function of the DAB.
D = D d
U o 0 = U o 0 U o 0
i L 1 r e a l = i L 1 r e a l I L 1 r e a l
i L 1 i m a g = i L 1 i m a g I L 1 i m a g
sin ( π D ) U o 0 = sin ( π D ) U o 0 + U o 0 sin ( π D ) cos ( π D ) + U o 0 cos ( π D ) sin ( π D ) = sin ( π D ) U o 0 + U o 0 sin ( π D ) + U o 0 cos ( π D )
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G open loop = [ C ( sI A ) 1 B + D ]
G open loop = 4.5 × 10 4 s 2 + 4.15 × 10 9 s + 6.072 × 10 15 s 3 + 92398 s 2 + 1.798 × 10 10 + 6.264 × 10 12

3.3. Output (DC-AC) stage

The DC-AC stage architecture and the equivalent diagram are presented in Figure 6 (a) and Figure 6 (b), respectively. Based on Figure. 6 (b), the KVL is applied and can be expressed as Eq. (42), followed by Eqs. (43) and (44). Further, the voltage across the capacitor and current through the load and capacitor are presented in Eqs. (45), (46), and (47), respectively. Eq. (48) denotes the inverter output. Thereafter, a small signal change was applied to Eq. (44), Eqs. (49) and (50) are obtained. Then, applying the Laplace transform to Eq. (50) yields Eq. (51), and the ratio is presented in Eq. (52). In order to smoothen the output signal, a filter circuit is added, which is formulated in Eq. (53), and the final equation is given in Eq. (54). Further, using Eqs. (52) and (54), the obtained equations are Eqs. (55) and (56). Eq. (57) represents the closed-loop transfer function of the output (DC-AC) stage converter. However, this closed-loop transfer function is designed without a controller. Thus, to design a controller with this transfer function, MATLAB SISOTOOL is used, and the final transfer function becomes Eq. (58). Subsequently, the state space parameters are found using Eq. (58), and then controllability and observability are tested in Section 4.
U inv ( t ) u ( t )   L ac di ac ( t ) dt   U c ( t ) = 0
L ac   di ac ( t ) dt =   U inv ( t ) u ( t ) U c ( t ) where u ( t ) = { 1 ,     U inv = U 0     0 ,                               U inv = 0     1 ,           U inv = U 0  
L ac di ac dt = U 0 ( t ) U c ( t )
U c ( t ) = 1 C ac i C ( t ) dt
i C ( t ) = i ac ( t ) i load ( t )
i load ( t ) = U load   Z
U inv ( t ) u ( t ) = U 0 ( t ) = D 2 ( t ) U out
L ac d ( i ac + i ac ) dt = ( U 0 ( t ) + U 0 ( t ) ) ( U C ( t ) + U C ( t ) )
L ac d ( i ac ) dt = ( U 0 ( t ) ) ( U C ( t ) )
sL ac ( i ac ) = U 0 ( s ) U C ( s )
U 0 ( s ) U C ( s ) = 1 + s 2 L ac C ac i ac ( s ) i C ( s )
i ac ( s ) = i C ( s ) + i Load ( s ) = i C ( s ) + U C ( s ) Z
i ac ( s ) i C ( s ) = 1 + 1 sC ac Z
i C ( s ) U C ( s ) = sC ac 1 + s 2 L ac C ac   + sL ac Z
Thus , G op = 0.00312 s 3.9 × 10 9 s 2 + 8.113 × 10 4 s + 1
G op = 0.00312 s 3.9 × 10 9 s 2 + 8.113 × 10 4 s + 1
G op ( Con ) = 0.1647 s 3.047 × 10 14 s 3 + 6.338 × 10 9 s 2 + 4.195 × 10 4 s
The state-space matrix of the above-mentioned equation is given as
  A = 1 × 10 10 [ 0.000 1.3768 0 0 0 0 0 0 0 ]   B = [ 1   0   0 ] C = 1 × 10 12   [ 0 0 5.4053 ]   D = [ 0 ] 1 × 1

4. Results and discussion

The overall model of the system is developed by concatenating the models of individual parts.

4.1. Time domain and frequency domain analysis

The proposed SST model is designed and analyzed in terms of time response, frequency response, and state-space characteristics. The time response analysis is conducted by the root locus technique, which determines the absolute stability and shows the location of poles or zeros in the s-plane. This technique also determines the physical performance of the model when the gain of the input to the plant is changed from 0 to   . The technique is advantageous in controller design because it is organized and saves energy and time. This study is limited to the linearized model, and both eigen analysis and frequency domain testing are applied to the linear model. In addition, time-domain analysis is studied.
Input stage numerical study: To ensure the stable operation of the system, a controller is added through MATLAB SISIOTOOL, given in Eq. (59) and (60) for G in and G vi , respectively. The overall closed-loop transfer function of the input stage converter is given by Eq. (61).
PI in = ( 3.825 × 10 6 + 6.5 × 10 6 s ) s
PI vi = 2.7 × 10 6 + 0.0002592 s s
G input = 2.9 × 10 6 s 2 + 1.717 × 10 6 s + 1.76 × 10 8 7.65 × 10 6 s 4 + 6.5 × 10 6 s 3 + 6.69 × 10 6 s 2 + 1.717 × 10 6 s + 1.76 × 10 8
A = [ 0.8497 0.8745 0.2244 0.0023 1 0 0 0 0 1 0 0 0 0 1 0 ]   B = [ 1 0 0 0 ] C = [ 0 0.3791 0.2244 0.0023 ] D = [ 0 ]
Input stage controllability and observability test: To test the system controllability and observability, the controllable matrix (Mc) and observable matrix (Mo) can be measured, which are expressed in Eq. (62) and Eq. (63), respectively, while their corresponding values are given below. Given the matrices M c and M o , the ranks of both are 4, which signifies the system is controllable and observable because the ranks of matrics (Mc and Mo) are the same as 4.
M c = [ B   AB   A 2 B   A 3 B   ]
M o = [ C C A C A 2 C A 3 ]
M c = [ 1 0.8497 0.1526 0.6482 0 1 0.8497 0.1526 0 0 1 0.8497 0 0 0 1 ] M o = [ 0 0.3791 0.2244 0.0023 0.3791 0.2244 0.0023 0 0.0977 0.3292 0.0851 0.0009 0.2462 0.0003 0.0210 0.0002 ]
Isolation stage controllability and observability test: To test the system controllability and observability, the controllable and observable matrices as M c and M o respectively, and the values are given below.
M o = 1 × 10 17 [ 0.0000 0 0 0.0000 0.0000 0.0000 6.6707 1.6839 4.5691 ] 3 × 3 M c = 1 × 10 18 [ 0.0000 0.0000 0.0053 0.0000 0.0000 1.3348 0.0000 0.0000 1.5723 ] 3 × 3
From the Mc and Mo, the ranks of both are 3, which signifies the system is controllable and observable. To ensure the stability of the system and its closed-loop function, a feedback controller and a filter circuit must be added, which is expressed in Eq. (64). The corresponding state-space parameter ( A ,   B ,   C ,   and   D ) and followed by the test matrix (controllable and observable matrix) of the isolation stage are shown below, which is also controllable and observable because the rank of the matrix is the same as that of the test matrix. Further, the closed-loop transfer function of the proposed DAB converter is expressed in Eqs. (65) and after the assigned value, it is presented in Eq. (66).
G filter = 0.001362 s + 1 4.916 × 10 6 s 2 + 0.04229 s
The corresponding A, B, C, and D matrix are:
A = 1 × 10 3 [ 8.851 0 0.0010 0 ] 2 × 2 B = [ 1 0 ] C = 1 × 10 5 [ 0.0028 2.0300 ] D = [ 0 ]
M c = 1 × 10 3 [ 0.0010 8.5851 0 0.0010 ] M o = 1 × 10 6 [ 0.0003 0.2030 2.1707 0 ]
G closed loop = G converter × G filter
G closed loop = 61.29 s 3 + 5.697 × 10 6 s 2 + 8.275 × 10 12 s + 6.072 × 10 15 4.926 × 10 6 s 5 + 0.4974 s 4 + 9.25 × 10 4 s 3 + 7.914 × 10 8 s 2 + 2.649 × 10 11 s
Output stage controllability and observability test: This sub-section is similar to Sections 3.1.1 and 3.2.1. As in Eqs. (62) and (63), M c and M 0 are controllable and observable matrices, and the values are given below. The ranks of these matrices are 3, which signifies the system is controllable and observable, which subsequently means that the output stage is controllable and observable.
M c = 1 × 10 10 [ 0 0.000 2.950 0 0 0.000 0 0 0 ]   M 0 = 1 × 10 22 [ 0 0 0 0.000 0 0 0.0001 7.4418 0 ]  
The stability criterion is shown in Table 1. Further, the performance index is measured through frequency domain analysis and presented in Table 2 for the input, isolation, and output stages.
The Bode diagram reflects the variation in magnitude and phase with respect to frequency level at a log scale. Various parameters, such as GM, PM, ωcg, and ωcp, can be measured from the Bode plot. Thus, system stability margins can be determined. The Nyquist plot reflects the relationship between the imaginary part of the closed-loop transfer function and the radial frequency (ω) in the real axis with the variation in 'ω' from zero to infinite in the polar coordinate. This plot determines the absolute and relative stability even if the system has delays in practical assumption. The plot also provides information such as GM, PM, BW, f p e a k , and g p e a k . The Nichols plot is the extension of the polar plot. In this plot, magnitude and phase-angle loci at log scale versus phase diagram are in the imaginary and real axes. The location of poles and zeros of the system is presented in the pole-zero plot, and the eigenvalue of each converter in the form of a graph is depicted in Figure 7, Figure 8 and Figure 9 for the input, isolation, and output stages, respectively.

4.2. Simulation results analysis

In this section, the simulation results of the three-stage SST are shown. The source voltage, source current, load voltage, load current, and DC-link voltage after completion of SST simulation are shown in Figure. 10. The behavior of the input remains the same, even if the load side transient is disturbed. Thus, SST provides excellent isolation through the DAB converter and maintains the same phase angle at the input stage.

4.3. Hardware-in-the-loop (HIL) validation

Furthermore, the Simulink model of SST has been built and executed in real-time simulation using the OPAL-RT simulator. The specification of the real-time digital simulator is OP5707XG, Intel® Xeon® processing cores with the power of a Xilinx® Virtex®-7 FPGA. The RT lab 2020 is installed on our laptop with a specification of 13th Gen Intel(R) Core(TM) i7-1355U 1.70 GHz, 64-bit operating system.
This key action marks a major advancement in the pursuit of accuracy and real-world application. The incorporation of OPAL-RT as hardware-in-the-loop (HIL) simulation is crucial and facilitates the transition between virtual and physical systems. The proposed SST model has been developed with hardware synchronization using OPAL-RT, creating an environment closely resembling real-world situations.
Figure 11 represents the HIL setup, where the SST model has been developed using RT Lab (a), synchronized through the OPAL-RT simulator (b), and the output can be observed on an oscilloscope (c). Furthermore, the performance of the HIL model of SST is presented in Figure 12. The input voltage and current are displayed in Figure 12 (a) and (b), while the output voltage and current are shown in Figure 12. (c) and (d), respectively. The DAB output can be observed in Figure. 12 (e). Based on the HIL results, it can be concluded that it exhibits the exact performance of the Simulink model, as presented in Figure. 10. The implementation of the proposed SST Simulink model with OPAL-RT for HIL simulation has been successfully validated, representing a significant accomplishment in our research and development work. This makes the proposed SST model more credible and ensures that our considerations are not limited to the virtual world but have relevance to the complexities of the actual world.

5. Conclusions

In this study, a state-space model is established to measure the stability of each converter stage for determining the system performance with and without a controller. The analysis is conducted in three phases. In an initial attempt, the state-space model of the converters is developed and expressed in terms of state-space parameters (A, B, C, and D) and is tested over controllability and observability matrices for measuring the system state. The transfer function model is formulated from the state-space parameters and applied to the frequency and time domain analysis to draw the Bode plot, Nyquist, Nichols, and root locus plot. On the basis of these plots, the stability, DC gain, peak resonant, and eigenvalue of the system are measured. Further, the Simulink design is simulated, and the results are provided, validating the systems' characteristics and seen as smooth performances. Finally, the Simulink model has been validated using a real-time digital simulator, such as OPAL-RT, which is considered an HIL simulation, and its performance exactly matches the simulation results.
This study has particularly drawn attention to the transient performance and the stability of the system, which can be analyzed using the proposed approach, such as the state-space and transfer function-based model. The proposed SST model can be implemented in different applications. In particular, in distribution system applications, it has minimal impact on voltage disturbance and can manage the fluctuation caused by intermittent sources, like solar and wind. With these features, the SST can play an essential smart component to make it a resilient distribution system.

Author Contributions

Conceptualization, D.K.M. and M.H.A.; methodology, D.K.M.; software, D.K.M.; validation, D.K.M., S.P, and S.K.S; formal analysis, D.K.M., M.E and L.L.; investigation, D.K.M., M.E. and S.K.S.; resources, D.K.M. and J.Z; data curation, D.K.M.; writing—original draft preparation, D.K.M. and M.E; writing—review and editing, D.K.M. M.H.A, S.P, and J.Z; visualization, D.K.M.; supervision, L.L., and J.Z; project administration, D.K.M., and M.E; funding acquisition, D.K.M, JZ, and L.L. All authors have read and agreed to the published version of the manuscript.

Conflicts of Interest

The authors declare no conflict of interest.

Bibilogpahy

AC: Alternating current
BW: Bandwidth
DAB: Dual Active Bridge
DC: Direct current
D: Duty cycle
GM: Gain margin
HF: High frequency
MF: Medium frequency
PWM: Pulse width modulation
PM: Phase margin
SST: Solid State Transformer
MGs: Microgrids
N: Turns ratio
Z: Load
U: Voltage
F: Frequency
L: Leakage inductance
ɸ: Phase shift
db: decibel
SGs: Smart-grids
I : Identity matrix
U s : input voltage
U dc : dc link voltage
U m : peak ac input voltage
U inv = U 0 : inverter output voltage
U c : voltage across the capacitor
D : duty cycle
D 1 : averaged duty cycle
D 2 : output stage duty cycle
A small change in the duty cycle
K m : modulation index
R= resistance at the isolation stage
L f / L t f / L a c : Inductor at the input, isolation, and output stage
C f / C o / C a c : capacitor at the input, isolation, and output stage
Ltf & Rtf: Transformer equivalent inductance and resistance
i ls : input current
i C : current through capacitor
i load : load current
i C : current through inductor at the output stage
i ls ( t ) : change in input current
G in and G vi : current and voltage control loop transfer function of the input stage
G open loop : open loop transfer function of the isolation stage
G op   and   G op ( con ) : transfer function of the output stage without and with controller
G filter : feedback controller for filter circuit for the output stage
G closed loop = closed-loop transfer function of the output stage
g P I 1 and g P I 1 : PI controller for G in and G vi fs: switching frequency
U 0 :   voltage across the capacitor
i L : current through the inductor
M c   a n d   M o :   controllable and observable matrix
GM and PM: Gain and phase margin
BW: bandwidth
ωcg and ωcg: gain crossover and phase crossover frequency
f p e a k and   g p e a k : peak frequency and gain peak
K D C : DC gain

Appendix A

System parameter and its value
Input stage Isolation stage Output stage
U i n = 1.2 k V   r m s
U p e a k = 1.7 k V
L s = 15 m H
C f = 420 µ F
M o d u l a t i o n   i n d e x = 0.85
U d c =400V
Turns ratio n 1 : n 2 =1:1
Switching frequency=20kHz
C 0 = 0.0035 F
L t f = 0.00347 m H ,   R r f = 0.16 Ω ,  
R 0 = 210.52   Ω ,   P o u t = 16 k W
U 0 =200V
L a c = 1   m H
C a c = 7.8 µ F

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Figure 1. Three-stage SST architecture.
Figure 1. Three-stage SST architecture.
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Figure 2. (a) AC-DC stage architecture, (b) Equivalent diagram of AC–DC stage.
Figure 2. (a) AC-DC stage architecture, (b) Equivalent diagram of AC–DC stage.
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Figure 3. Control block representation of input stage.
Figure 3. Control block representation of input stage.
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Figure 4. (a) DC-DC stage architecture, (b) Equivalent diagram of DC-DC stage.
Figure 4. (a) DC-DC stage architecture, (b) Equivalent diagram of DC-DC stage.
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Figure 5. Inductance versus (a) frequency with a phase shift of 400 V, (b) power with a phase shift of 400 V (c) frequency with a phase shift of 200 V, (d) power with a phase shift of 200 V.
Figure 5. Inductance versus (a) frequency with a phase shift of 400 V, (b) power with a phase shift of 400 V (c) frequency with a phase shift of 200 V, (d) power with a phase shift of 200 V.
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Figure 6. (a) DC-AC stage architecture (b) Equivalent diagram of DC–AC stage.
Figure 6. (a) DC-AC stage architecture (b) Equivalent diagram of DC–AC stage.
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Figure 7. Input stage: (a) Bode plot, (b) Nyquist plot, (c) Nichols plot, (d) Root locus, (e) Pole–zero plot, (f) Eigen plot.
Figure 7. Input stage: (a) Bode plot, (b) Nyquist plot, (c) Nichols plot, (d) Root locus, (e) Pole–zero plot, (f) Eigen plot.
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Figure 8. Isolation stage (a) Bode plot, (b) Nyquist plot, (c) Nichols plot, (d) Root locus, (e) Pole–zero plot, (f) Eigen plot.
Figure 8. Isolation stage (a) Bode plot, (b) Nyquist plot, (c) Nichols plot, (d) Root locus, (e) Pole–zero plot, (f) Eigen plot.
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Figure 9. Output stage (a) Bode plot, (b) Nyquist plot, (c) Nichols plot, (d) Root locus, (e) Pole–zero plot, (f) Eigen plot.
Figure 9. Output stage (a) Bode plot, (b) Nyquist plot, (c) Nichols plot, (d) Root locus, (e) Pole–zero plot, (f) Eigen plot.
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Figure 10. (A) Source voltage. (B) Source current, (C) Load voltage (D) Load current, (E) DC-link voltage.
Figure 10. (A) Source voltage. (B) Source current, (C) Load voltage (D) Load current, (E) DC-link voltage.
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Figure 11. HIL setup for SST model validation.
Figure 11. HIL setup for SST model validation.
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Figure 12. Real-time validation results: (a) Source voltage. (b) Source current, (c) Load voltage (d) Load current, (e) DC-link voltage.
Figure 12. Real-time validation results: (a) Source voltage. (b) Source current, (c) Load voltage (d) Load current, (e) DC-link voltage.
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Table 1. Frequency response indices criteria.
Table 1. Frequency response indices criteria.
Parameter System
GM= +ve, PM= +ve Stable
GM= −ve , PM= +ve Unstable
GM= +ve , PM= −ve Unstable
Table 2. Frequency response indices of the input stage.
Table 2. Frequency response indices of the input stage.
Parameter Input stage Isolation stage Output stage
GM Inf Inf Inf
PM 80.0634 5.1306 5.1306
ωcg Inf Inf Inf
ωcp 0.8153 2.3237×106 2.3237×106
dbdrop −3.5 −3.5 −3.5
BW 1.0110 335.0966 -1.152×106
KDC 1 0 335.0966
fpeak 0.7069 33.5 0
gpeak 1.0534 335.0966 33.5
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