3.1. FPGA Tool Flow

• Synthesize the timing engine and other components of the static design.
• Routing constraints are used to fix SMs and wires for the Hand-Crafted experiment in 67 separate designs, while timing constraints are used to force different routes from the Vivado PNR tool in the Tool-Crafted experiment.
• TCL commands are used to create the DPR region, which is represented as a pblock in Vivado. The locked static design is used to maintain the exact same layout in all DPR designs created.
• PNR is run to join the static and DPR designs.
• The full bitstream is used to program the device, followed by any sequence of partial bitstreams created by this tool flow.

3.2. Delay Post-Processing Algorithm

• The programmable logic of the FPGAs is programmed with the full bitstream, followed by a sequence of partial bitstream programming operations. The timing engine measures both rising and falling delays of paths implemented within each of the partial bitstreams. The curves labeled 1) BaseRoute & RouteExt Raw Delay in Figure 5 show the rising path delays for the base route (black) and route extensions (blue) measured from the 34 FPGAs (falling delays are omitted). The acyonyms BR and RE refer to BaseRoute and RouteExtensions, respectively. We use the term Raw to refer to both sets.
• The RE and BR delays are calibrated to remove global process variations using a Global Process and Environmental Variation (GPEV) module. The GPEV module applies a pair of linear transformations given by Eqs. 1 through 4. The mean and standard deviation of the 134 Raw delays from each FPGA are computed and the Raw delays are standardized using Eqs. 1 and 3. A second linear transformation using 0.0 and 44.1 for ${\mu }_{ref}$, and ${\sigma }_{ref}$ (Eq. 4) is then applied to convert the standardized values back to a form similar to the original data (44.1 is the mean $\sigma$ across all FPGAs). The same ${\mu }_{ref}$ and ${\sigma }_{ref}$ are used for all devices in the second transformation, which effectively removes global performance differences while preserving within-die variations. Although difficult to observe, the variations in the rising delays across all FPGAs in the plot labeled 2) Compensate Raw Delays from Figure 5 are smaller than those from Step 1. We use the symbol ’F’ for FPGA, ’i’ for FPGA instance, ’c’ for calibrated and ’r’ for route in these equations. The GPEV calibrated delays are referred to as $B{R}_c$ and $R{E}_c$.
• The rising and falling path delays from the BaseRoute design are subtracted from the corresponding rising and falling path delays of the RouteExt designs in the graph labeled 3) Subtract BaseRoute delay of Figure 5. We refer to these delay differences as ${\mathrm{DVR}}_c$ and ${\mathrm{DVF}}_c$ (DV is an acronym for delay value). The delays of the ${\mathrm{DVR}}_c$ and ${\mathrm{DVF}}_c$ vary from 80 picoseconds (ps) to 1.8 nanoseconds (ns) across all 67 rise and fall delays.
• The final transformation is shown in 4) Remove DC bias. The ${\mathrm{DVR}}_c$ and ${\mathrm{DVF}}_c$ posses a DC bias that exists because the routes are not identically designed. The process of removing bias is accomplished by computing the mean delay of each ${\mathrm{DVR}}_c$ and ${\mathrm{DVF}}_c$ across all FPGAs and then subtracting this offset from the compensated raw delays. We use the symbol ’R’ here to refer to individual route extensions and ’x’ for the route extension number. Eq. 5 and 6 gives expressions for computing the rise and fall compensated raw delays without bias, annotated as ${\mathrm{DVR}/\mathrm{F}}_{co}$, with ’o’ referring to ’offset’.

  $${\mu }_{{\mathbf{F}}_i}=\frac{{\displaystyle \sum _{r=1}^{134}}{\mathrm{Raw}}_{i,r}}{134}$$

  (1)

  $${\sigma }_{{\mathbf{F}}_i}=\sqrt{\sum _{r=1}^{134}{({\mathrm{Raw}}_{i,r}-{\mu }_{{\mathbf{F}}_i})}^{2}133}$$

  (2)

  $${\mathbf{Z}}_{{\mathbf{F}}_i}=\frac{({\mathrm{Raw}}_{i,r}-{\mu }_{{\mathbf{F}}_i})}{{\sigma }_{{\mathbf{F}}_i}}$$

  (3)

  $${\mathrm{Raw}}_{{\mathbf{c}}_{\mathbf{i}}}={\mathbf{Z}}_{\mathbf{F}}i\ast {\sigma }_{ref}+{\mu }_{ref}$$

  (4)

  $${\mu }_{{\mathbf{R}}_x}=\frac{{\displaystyle \sum _{i=1}^{34}}{\mathrm{Raw}}_{c_{i,x}}}{34}$$

  (5)

  $${\mathrm{DVR}/\mathrm{F}}_{{\mathbf{co}}_{\mathbf{i},\mathbf{x}}}={\mathrm{Raw}}_{c_{i,x}}-{\mu }_{{\mathbf{R}}_x}$$

  (6)

3.3. Tool-Crafted Data Post-Processing

• The Raw DVR and DVF are plotted in the upper left graph, where we show the first 100 rising delays on the left and the first 100 falling delays on the right, both from the larger sets of 4096 values in each group. The vertical shift in the two data sets, with rising delays having smaller overall delays, illustrates a common process-related characteristic that p-channel (pull-up) devices are not well correlated with n-channel (pull-down) devices on the same FPGA. This pattern varies depending on the FPGA.
• In contrast to the Hand-Crafted algorithm, the second step involves subtracting the BaseRoute delays from the RouteExt delays. The first 100 DVR and DVF are plotted in the 2) DVR and DVF graph.
• In step 3, the 4096 DVR are randomly paired and subtracted from the 4096 DVF, as a means of doubling the level of entropy in the delay differences (DVD). Note that additional DVD can be created by other random pairing and differencing operations applied to the DVR and DVF groups, up to a total of ${\left(4096\right)}^2$ unique combinations.
• The GPEV operation is applied to the DVD to create ${\mathrm{DVD}}_c$, using Eqs. 1 through 4 with 4096 replacing 134, DVD replacing Raw and 28.0 replacing 44.1 for ${\sigma }_{ref}$.
• Step 5 converts the ${\mathrm{DVD}}_c$ to ${\mathrm{DVD}}_{co}$ by subtracting the mean $DV{D}_c$ delay from each of the individual $DV{D}_c$, using Eq. 5 and 6.
• The operation carried out in Step 6 is optional, and serves only to make the number of strong bits in the generated bitstrings approximately the same for each FPGA when a threshold is applied (described below). The scaling operation computes the average range of the variation in the ${\mathrm{DVD}}_{co}$ of each FPGA i and multiplies all ${\mathrm{DVD}}_{co}$ by a ratio that makes the ranges approximately equal for all devices. The ratios vary between 1.00 and 1.91 and illustrate that the level of random variations (entropy) in each FPGA is not constant. We refer to the delays shown in Step 6 as ${\mathrm{SDVD}}_{co}$ (’S’ for scaled) in the following.

3.4. Bitstring Generation Algorithm

4.1. Experimental Results: Hand-Crafted Design

4.2. Experimental Results: Tool-Crafted Design