Version 1
: Received: 30 August 2024 / Approved: 30 August 2024 / Online: 30 August 2024 (12:45:03 CEST)
How to cite:
Regoršek, Ž.; Gorkič, A.; Trost, A. Parallel Lossless Compression of Raw Bayer Images on FPGA-BASED High-Speed Camera. Preprints2024, 2024082230. https://doi.org/10.20944/preprints202408.2230.v1
Regoršek, Ž.; Gorkič, A.; Trost, A. Parallel Lossless Compression of Raw Bayer Images on FPGA-BASED High-Speed Camera. Preprints 2024, 2024082230. https://doi.org/10.20944/preprints202408.2230.v1
Regoršek, Ž.; Gorkič, A.; Trost, A. Parallel Lossless Compression of Raw Bayer Images on FPGA-BASED High-Speed Camera. Preprints2024, 2024082230. https://doi.org/10.20944/preprints202408.2230.v1
APA Style
Regoršek, Ž., Gorkič, A., & Trost, A. (2024). Parallel Lossless Compression of Raw Bayer Images on FPGA-BASED High-Speed Camera. Preprints. https://doi.org/10.20944/preprints202408.2230.v1
Chicago/Turabian Style
Regoršek, Ž., Aleš Gorkič and Andrej Trost. 2024 "Parallel Lossless Compression of Raw Bayer Images on FPGA-BASED High-Speed Camera" Preprints. https://doi.org/10.20944/preprints202408.2230.v1
Abstract
Digital image compression is applied to reduce camera bandwidth and storage requirements, but real-time lossless compression on a high-speed high-resolution camera is a challenging task. The article presents hardware implementation of a Bayer colour filter array lossless image compression algorithm on an FPGA-based camera. The compression algorithm reduces colour and spatial redundancy and employs Golomb-Rice entropy coding. A rule limiting the maximum code length is introduced for the edge cases. The proposed algorithm is based on integer operators for efficient hardware implementation. The algorithm is first verified as a C++ model and later implemented on Xillinx Zynq UltraScale+ device using VHDL. An effective tree-like pipeline structure is proposed to concatenate codes of compressed pixel data to generate a bitstream representing data of 16 parallel pixels. The proposed parallel compression achieves up to 56% reduction in image size for high resolution images. Pipelined implementation without any state machine ensures operating frequencies up to 320 MHz. Parallelised operation on 16 pixels effectively increases data throughput to 40 Gbit/s while keeping total memory requirements low due to real-time processing.
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
