Version 1
: Received: 5 September 2024 / Approved: 5 September 2024 / Online: 5 September 2024 (12:10:44 CEST)
How to cite:
KADBE, P. K.; Markande, S. Efficient Design of Reversible Adder and Multiplier Using Peres Gates. Preprints2024, 2024090455. https://doi.org/10.20944/preprints202409.0455.v1
KADBE, P. K.; Markande, S. Efficient Design of Reversible Adder and Multiplier Using Peres Gates. Preprints 2024, 2024090455. https://doi.org/10.20944/preprints202409.0455.v1
KADBE, P. K.; Markande, S. Efficient Design of Reversible Adder and Multiplier Using Peres Gates. Preprints2024, 2024090455. https://doi.org/10.20944/preprints202409.0455.v1
APA Style
KADBE, P. K., & Markande, S. (2024). Efficient Design of Reversible Adder and Multiplier Using Peres Gates. Preprints. https://doi.org/10.20944/preprints202409.0455.v1
Chicago/Turabian Style
KADBE, P. K. and Shriram Markande. 2024 "Efficient Design of Reversible Adder and Multiplier Using Peres Gates" Preprints. https://doi.org/10.20944/preprints202409.0455.v1
Abstract
This paper details the approach to the efficient design and optimization of reversible adder and multiplier utilizing Peres gates which is a three input, three output gate. Peres gates are recognized for their universality and energy efficient properties and present an intriguing option for constructing reversible circuits. Reversible logic are characterized by its ability to uniquely determine input states from output states. The design methodology involves a cascading arrangement of Peres gates each performing a reversible XOR operation on corresponding bits of the input numbers and the carry out from the preceding stage. The paper presents a detailed schematic representation, simulation results and analysis of the proposed designs of different adders and multipliers showcasing their potential for reversible applications. The integration of Peres gates in the adder and multiplier design signifies a step forward in the exploration of reversible logic circuits and their applications in contemporary computing paradigms. The overall hardware reduction is the main achievement of this research in terms of quantum cost.
Keywords
Carry Save Adder; Carry Skip Adder; Look Ahead Carry Adder; Multiplier; Peres Gates; Ripple Carry Adder; Reversible Logic
Subject
Engineering, Electrical and Electronic Engineering
Copyright:
This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
