1. Introduction

2. Test-Pattern Measurements for the Distributed Power Amplifier Design

2.1. Active Devices

The circuits developed in this study are designed to operate up to the millimeter-wave frequency band. Since the wavelength in this band is less than one millimeter, circuits for millimeter-wave signals require a different approach than conventional electronic circuits. It is necessary to consider parasitic capacitance and parasitic inductance, which were previously excluded from analysis, within the context of millimeter-wave frequencies. These parasitic components must be included in the equivalent model, as they will affect the high-frequency characteristics of the transistor. The size and layout of the transistor can also influence the magnitude of the parasitics, which can significantly alter high-frequency performance. Therefore, selecting a transistor prototype with optimal high-frequency characteristics is crucial before designing a millimeter-wave communication circuit.

In previous studies [6,7], the RF performance of various transistor layout structures was compared. However, there is a need to validate transistor layout structures for power amplifier designs in CMOS processes with a different back end of line (BEOL) than at that time. This study compares the high-frequency characteristics of transistors based on their size and layout structure. S-parameter measurements are conducted using a vector network analyzer (VNA) to investigate these characteristics, and transistors are designed and fabricated using a commercial 28 nm CMOS process.

Figure 2. RF transistor layout of (a) symmetry-typed and (b) ring-typed structure (both are 2 × 64 μm LVT NFET_RF devices).

Figure 2. RF transistor layout of (a) symmetry-typed and (b) ring-typed structure (both are 2 × 64 μm LVT NFET_RF devices).

For this circuit design, we developed test patterns for key passive and active devices during the last multi-project wafer (MPW) run. Figure 2a,b show the RF transistor layouts of symmetrical and ring-type structures. Both have the same dimensions of 2 (unit gate width) × 64 (number of gate fingers) μm, and the device type is low threshold voltage RF n-channel field-effect transistor (LVT_NFET_RF). Figure 3a,b present the maximum available gain/maximum stable gain (MAG/MSG) and S-parameters as functions of layout structure. MAG/MSG typically represents the maximum power gain that a transistor can produce at a specific frequency and can be calculated using the S-parameters, as shown in Equations (1) – (2b). If the stability factor is greater than or equal to 1, it is calculated as MSG; if it is less than or equal to 1, it is calculated as MAG [8].

$$\mathrm{K}={\displaystyle \frac{\left(1-{\left|S11\right|}^2-{\left|S22\right|}^2+{\left|S11·S22-S12·S21\right|}^2\right)}{\left(2·\left|S12·S21\right|\right)}}$$

(1)

$$\mathrm{M}\mathrm{A}\mathrm{G}={\displaystyle \frac{\left|S_{21}\right|}{\left|S_{12}\right|}}\left(K-\sqrt{K^2-1}\right)\left(K>1\right)$$

(2a)

$$\mathrm{M}\mathrm{S}\mathrm{G}={\displaystyle \frac{\left|S_{21}\right|}{\left|S_{12}\right|}}\left(\mathrm{K}<1\right)$$

(2b)

Specifically, we compare the characteristics at 28 GHz and 40 GHz, both of which are 5G communication frequencies. As shown in Figure 3a, for the 2 × 32 μm configuration, transistors with symmetrical structures exhibit higher values by about 1.5 dB at 28 GHz and about 3.1 dB at 40 GHz. For the 2 × 64 μm configuration, the symmetrical structure shows 3 dB to 4 dB higher MAG/MSG characteristics at both 28 GHz and 40 GHz, respectively. This indicates that the symmetrical layout has smaller parasitic components than the ring structure. This is likely due to the shorter drain feed line and reduced length of the gate ring in the symmetrical layout, resulting in smaller capacitance and less resistance from the surrounding source and drain [6]. In fact, when comparing the S-parameters shown in Figure 3a,b, the symmetrical type has larger trajectories for S11 and S22, and smaller magnitudes for S12 compared to the ring type, indicating that the symmetrical type has lower gate/drain resistance and parasitic capacitance. This confirms that the symmetrical layout exhibits better RF characteristics.

Meanwhile, the MAG/MSG of different transistor sizes are compared, as shown in Figure 4. The fabricated sizes are 1 × 32 μm, 2 × 32 μm, and 2 × 64 μm, all of which have ring-type layouts and are of the LVT_NFET_RF kind. Generally, larger transistor sizes lead to greater transconductance ($g_m$), resulting in higher small-signal gain at low frequencies; However, parasitic capacitance significantly affects losses at high frequencies, leading to lower gain. The MAG/MSG comparison indicates that the 1 × 32 μm and 2 × 32 μm configurations exhibit similar performance up to 35 GHz, with the 1 × 32 μm size showing better MAG/MSG from 40 GHz onward. In contrast, the 2 × 64 μm configuration shows a clear degradation in MAG/MSG from 20 GHz onward. While the 1 × 32 μm is advantageous when considering only small-signal gain, the 2 × 32 μm size is preferable when considering P_out, as it has a larger current and its MAG/MSG does not drop significantly until 40 GHz.

Based on these measurement results, a 2 × 32 μm symmetrical LVT_NFET_RF with MAG/MSG greater than 10 dB at 40 GHz is selected as the unit transistor for the distributed power amplifier (DPA).

3. Distributed Power Amplifier Design and Results

4. Conclusions

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