A Cascade Fractional-N Synthesizer Topology of DLL and Frequency Multiplier for 5G+ Communication Systems

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A Cascade Fractional-N Synthesizer Topology of DLL and Frequency Multiplier for 5G+ Communication Systems

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Submitted:

02 October 2024

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02 October 2024

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Abstract

This study presents a synthesizer topology based on a DLL and programmable frequency multiplier for 5G+ communication systems. The proposed synthesizer comprises a 512-phase DLL, an intermediate frequency generator (IFG), and an RF frequency multiplier (RFFM). The 512-phase DLL provides 512 delayed pulses through a chain of 256 delay units and single-to-differential complementary converters (S2DCs). The IFG comprises I/Q-multiplexers, I/Q-accumulators, an XOR, and an S2DC. The I/Q-multiplexer outputs switch to the phase lag or lead waveforms at every rising or falling edge of the outputs, which makes the I/Q-multiplexer output frequency, fMX, programmable. The IF, fIF, is two times fMX, and fIF is up-converted to RF, fRF, through the RFFM. When reference clock frequency, fref is 156.25 MHz, the fIF range is 156.863–312.5 MHz and the fRF dynamic range is approximately 1.89–9.96 GHz. The channel resolution range is 3.698–38.609 MHz. Consequently, the proposed synthesizer provides a wide 134 % output frequency bandwidth and a finer channel resolution smaller than fref. The presented synthesizer is fabricated in a 65-nm CMOS process. The total power consumption is 15 mW, and the rms jitter integrated from 12 kHz to 20 MHz measured as 83 fs.

Keywords:

Subject: Engineering - Electrical and Electronic Engineering

1. Introduction

The quality factors of inductor (L) and capacitor (C) are small at the millimeter wave (mmWave). Therefore, designing an ultra-low phase noise (PN) LC voltage-controlled oscillator (VCO) that adheres to the stringent integrated jitter specification for the beyond 5G communication systems is tough. The cascade local oscillator (LO) generator structures of a lower-frequency synthesizer and a frequency multiplier (FM) have been recently published [1,2,3,4,5] to accomplish the jitter performance. The main goals of the lower-frequency synthesizer are to provide the best in-band phase noise (PN) and the finest channel resolution performances.

A multiplying delay-locked loop (MDLL), a subsampling phase-locked loop (SSPLL), and an injection-locked PLL (ILPLL) are good candidate topologies to achieve ultra-low in-band PN. Figure 1(a) shows a phase edge combined (EC)-based MDLL block diagram. Output frequency (f_out) can be expressed as N×f_in/2, where N is an even integer number of delay cells in a voltage-controlled delay line (VCDL). Therefore, the MDLL channel resolution would be f_in. The biggest advantage of the MDLL is that it is free from jitter accumulation, which will improve the in-band PN. However, N is strictly difficult to program because the delay unit number in a VCDL must be changed. Therefore, its channel programmability is limited [6,7,8,9].

Both the SSPLL and ILPLL (Figure 1(b) and Figure 1(c)) have the same channel resolution (f_in) but require extra frequency tracking loops (FTLs) for locking the output frequency as N×f_in. After the target frequencies are tuned, the FTLs are turned off, and their lock states are maintained by a subsampling phase detector (SSPD) for the SSPLL and cascade connection of a digitally-controlled delay line (DCDL) and a pulse width controller for the ILPLL. Therefore, their in-band PNs will be improved because in-band PN sources are no longer multiplied by N² when transferred to the PLL outputs [10,11,12]. However, neither the SSPLL nor the ILPLL is suitable for high-magnitude multiplication, N, because it is difficult to design a reliable SSPD and DCDL as N is increased [13,14,15,16]. Consequently, the number of possible programmable channels is also restricted.

This paper presents a new cascade topology of a DLL-based synthesizer and an FM for a lower-frequency synthesizer. The DLL-based synthesizer consists of a 512-phase DLL and an intermediate frequency generator (IFG), providing a wide IF band. The IF band is up-converted to the RF band by the programmable high-frequency multiplication factor (FMF) RFFM. Therefore, the proposed synthesizer can provide ultra-low in-band PN, a channel resolution that is finer than the input frequency (f_in), ultra-low out-band PN, and a wide frequency band. The proposed synthesizer is fabricated in a 65-nm CMOS process, and the active die area is 0.6 mm². The total power consumption is 15 mW without counting a 50 Ω driving amplifier (DA) power consumption. Recent 5G LO research papers have achieved their rms jitter performances while using signal generators as reference clocks. However, our main purpose is to implement the optimum LO module solution for 5G⁺ wireless communication systems composed of the proposed synthesizer and currently available state-of-the-art reference external oscillators. When a 156.25 MHz micro-electro-mechanical systems (MEMS) differential oscillator (SiT9501) is applied as the reference clock, the LO module output frequency range is 1.88–9.96 GHz, and its channel resolution range is 3.698–38.609 MHz. The integrated rms jitter from 12 kHz to 20 MHz is 83 fs.

The rest of this paper is organized as follows: In section II, a new synthesizer topology is introduced. Its components are explained as well as their functionalities. Then, the proposed synthesizer output frequency range and channel resolution equations are presented. Finally, the synthesizer’s phase noise analysis and the benefits are presented. Section III shows core building block schematics. The core circuitries are analyzed and verified through simulations. Also, the design procedure for the target output frequency range is talked about in detail. Furthermore, the synthesizer’s adjacent harmonic rejection ratio analysis and simulation are presented last. The proposed synthesizer chip fabrication and printed circuit board (PCB) environment for testing the chip are shown in Section IV. Moreover, the synthesizer’s power consumption is summarized, and the DA output matching and capacitor bank (C_bank) calibration are discussed. Finally, the test measurements of core specifications are reported. The summary and comparative analysis with recently published synthesizers are presented in Section V.

2. Topology, Analysis, And Frequency Range

2.1. Synthesizer Topology, RF Range, and Channel Resolution

The proposed synthesizer consists of three subsidiary blocks (blue-color boxes): a 512-phase DLL, an IFG, and an RFFM as shown in Figure 2. In terms of functionality, the synthesizer can be divided into two blocks. One is an IF synthesizer consisting of the 512-phase DLL and IFG, and the other is a programmable RFFM.

The DLL’s components are a differential-to-single (D2S) buffer, a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage-controlled delay line (VCDL), and 256-phase single-to-differential complementary converters (256-S2DCs). The external oscillator frequency is denoted by f_ref, and its differential outputs are converted to V_MS through the D2S. The frequency of V_MS is f_MS (= f_ref), driving the PFD and VCDL. And, the VCDL is composed of a cascade chain of 256 delay units (DUs). An inverter (red) is inserted at the VCDL output to make it half-period locked, and its output (V_del) is fed to the other PFD input. The phase difference between V_MS and V_del is manipulated by the PFD+CP, which adjusts V_CT to control the delay of all the DUs simultaneously. When the phases of V_MS and V_del are locked, V_del is delayed by T_MS/2 from the rising edge of V_MS, where T_MS (= 1/f_MS) is the period of V_MS. Therefore, each DU’s delay, t_d, is uniformly equal to T_MS/512. An S2DC comprises two XORs: one XOR input is connected to a power supply, and the other XOR input is connected to a ground as shown in the dotted box of Figure 3(a). Figure 3(b) shows that the 256 different phase (D₁–D₂₅₆) pulses are expanded to 512 different phase (P₁–P₅₁₂) pulses through the 256-S2DCs.

The IFG consists of I/Q-multiplexers, I/Q-accumulators, an XOR, and an S2DC. All digital bits of A₉–A₁, Zy₉–Zy₁, and Zx₉–Zx₁ are programmable. After the DLL is locked, the accumulators add or subtract the input magnitude (A₉–A₁) from the previous values (Zy₉–Zy₁ or Zx₉–Zx₁). Depending on the accumulator output state of Y₉–Y₁ (or X₉–X₁), V_Q (or V_I) is switched to the P_M multiplexer input, where M is equal to the magnitude of Y₉–Y₁ (or X₉–X₁). For example, when the magnitude of Y₉–Y₁ = 1, V_Q is connected to P₁. V_Q and V_I drive the I/Q-accumulator’s D-flip-flops (DFFs) and XOR gate of generating V_IF. Depending on a feedback clock control (C_FC) state, V_Q (or V_I) is connected to either the left or right accumulator’s DFF. By applying the appropriate initial states of Zy₉–Zy₁ and Zx₉–Zx₁, the time delay between V_Q and V_I can be either T_MX/4 or (T_MX/4)–t_d. T_MX is the V_Q (or V_I) pulse period. The consequent V_IF’s fundamental frequency (f_IF) = 2×f_MX, where f_MX = 1/T_MX.

To visualize simple examples of how to vary f_IF, the multiplexer input phases are set to 16. As shown in Figure 4(a), P₁–P₁₆ waveforms are uniformly delayed by t_d (= T_MS/16). When the magnitude (AC_M) of A₉–A₁ is programmed as 6, and V_Q (or V_I) is switched to the phase lead signal at its rising and falling edges, the shift of V_Q (or V_I) would follow as the sequence P₁₆, P₁₀, P₄, P₁₄, P₈, P₂, P_12, P₆, and P₁₆. By combining the sequence, the high and low state durations of V_Q are reduced by 6t_d, which results in a 50% duty cycle 4t_d period pulse as indicated by the purple pulse at the bottom of Figure 4(a).

Unlike the previous phase shift pattern, V_Q and V_I might be switched to the phase lag signal. In addition, V_Q might be updated by V_I, and V_I might be updated by V_Q. Figure 4(a) shows V_Q and V_I shift sequences (blue and red) when AC_M = 1. Initially, V_I and V_Q are connected to P₇ and P₁₀. V_Q is switched to P₁₁ at the first rising edge of V_I, while V_I is switched to P₈ at the first rising edge of V_Q. The second phase shift of V_Q from P₁₁ to P₁₂ happens at the first falling edge of V_I. Moreover, V_I is switched to P₉ at the first falling edge of V_Q. By continuously updating in the just mentioned method, the phase shift sequence of V_I (V_Q) would be P₇ (P₁₀), P₈ (P₁₁), P₉ (P₁₂), P₁₀ (P₁₃), and P₁₁ (P₁₄). The final pulses of V_I and V_Q are 50% of the duty cycle and their period would be 18t_d because high and low state durations are increased to 9t_d at each rising and falling edge from 8t_d.

Figure 4 (b) shows all waveforms of V_Q and V_I for AC_M = 2, 3, 4, 5, and 6 when V_Q and V_I are shifted to the phase lag signal. The waveforms of V_Q and V_I shifting to the phase lead signal waveforms for AC_M = 1, 2, 3, 4, and 5 are shown in Figure 4(c). All V_Q and V_I waveforms are 50% duty cycle pulses. However, V_IFs are 50% duty cycle pulses (Figure 5(a)) when the period of V_Q and V_I (T_MX) is 4t_d, 8t_d, 12t_d, 16t_d, 20t_d, 24t_d, and 28t_d. Otherwise, the duty cycle (D_cycle) of V_IF would be expressed as

D_{c y c l e} = \frac{0.25 T_{M X} \pm 0.5 t_{d}}{0.5 T_{M X}} = \frac{1}{2} \pm \frac{t_{d}}{T_{M X}},

(1)

as shown in Figure 5(b). If t_d is reduced and T_MX is increased, the duty cycle offset (t_d/T_MX) would be close to zero.

Considering the previous example (P₁–P₁₆), T_MX would be t_d × (512±2AC_M). Because T_MS = 512×t_d, T_MS/T_MX can be expressed as 512/(512±2AC_M). Therefore, f_IF can be derived as

f_{I F} = 2 f_{M X} = 2 f_{M S} \frac{512}{512 \pm {2 A C}_{M}},

(2)

where AC_M can be programmed to any integer between 0-254. The proposed synthesizer output frequency can be expressed as

f_{R F} = {R F}_{F M F} f_{M S} \frac{1024}{512 \pm 2 {A C}_{M}},

(3)

where RF_FMF is the RFFM’s FMF. Replacing AC_M as AC_M+1 in (3) and subtracting it from (3), RF channel resolution (Δf_RF) between AC_M and AC_M + 1 is expressed as

{∆ f}_{R F} = {R F}_{F M F} f_{M S} \frac{2048}{(512 \pm 2 {A C}_{M}) (512 \pm 2 {A C}_{M} + 2)} .

(4)

The Δf_RF would be finer as the denominator of (4) is increased.

Applying f_MS = 156.25 MHz for AC_M = 1–254, the f_IF range is simulated as 156.86–311.28 MHz when V_I (V_Q) switches to the phase lag pulse. For V_I (V_Q) shifting to the phase lead pulse, the f_IF span will range from 313.73 MHz to 40 GHz. However, f_IF is intentionally limited to 311.28 MHz for a fine channel resolution in this paper. RF_FMF can be programmed as any even number among 12-32. By setting RF_FMF = 32 and AC_M = 1, f_RF will be 9.96 GHz. A 1.88 GHz f_RF can be generated by programming RF_FMF = 12 and AC_M = 254. The consequent Δf_RF range is 3.698 -38.609 MHz according to (4).

2.2. Phase Noise Analysis and no Jitter Accumulation

The proposed synthesizer PN sources are shown in Figure 6, where θ_XO, θ_PC, and θ_DL are the PN spectral densities (PNSDs) of the reference clock, the PFD+CP, and the VCDL, respectively. K_PC (= I_cp/(C_LS)) and K_DL are the PFD+CP and VCDL gains. K_SYN is the total FMF from f_ref (= f_MS) to f_RF as shown in Figure 2. T_MS (= 1/f_MS) is much less than the DLL time constant such that exp(-ST_MS) = 1 [17]. Therefore, the proposed synthesizer output PNSD, θ_SYN, can be derived as

θ_{S Y N} (s) = \{θ_{X O} + {θ_{P C} [H_{l} (s)]}^{2} + θ_{D L} {[H_{h} (s)]}^{2}\} K_{S Y N}^{2},

(5)

where

H_{l} (s) = \frac{I_{C P} K_{D L}}{I_{C P} K_{D L} + S C_{L}} a n d H_{h} (s) = \frac{S C_{L}}{I_{C P} K_{D L} + S C_{L}} .

(6)

According to (5), the proposed synthesizer has no low-pass filter effect on θ_XO. Therefore, the integrated rms jitter of θ_XO should be less than the target jitter such as 100 fs from 12 kHz to 20 MHz of the 28 GHz carrier frequency [18]. The target 100 fs integrated rms jitter is translated as 0.005625˚ at a 156.25 MHz crystal oscillator, which was stringent to achieve a decade ago. Fortunately, ultra-low jitter oscillator products have been recently released with a few hundred frequency range MHz. For example, SiT9501 yields a 70.629 fs rms jitter integrating a 12 kHz–20 MHz offset bandwidth when the operation frequency is 156.25 MHz.

As noted in (6), the noise transfer function (NTF) of the θ_PC, H_l(S), is a low-pass filter (LPF). Unlike other synthesizers such as the CPPLL, SSPLL, and ILPLL, both values of I_cp and C_L can be freely selected because the presented DLL has no stability constraint. Therefore, the effect of θ_PC on the presented synthesizer output can be minimized by manipulating I_cp and C_L as much as possible. On the contrary, H_h(S), the NTF of θ_DL is a high-pass filter (HPF) so that lower-frequency PN sources such as flicker noise would be filtered out.

While VCO output jitters in all other PLLs are accumulated until they are fixed by the reference clock as shown in Figure 7, the proposed synthesizer has no jitter accumulation because of no oscillator. Furthermore, a good design FM output’s integrated jitter would be close to the input jitter. In contrast, a typical synthesizer’s integrated jitter is severely degraded by a VCO out-band PN, particularly, for wide data bands.

The absence of a loop stability constraint and VCO makes the proposed synthesizer provide a relatively wide output frequency range, comparable jitter, and a finer channel resolution than f_ref, compared with the state-of-the-art synthesizers proposed in recently published papers [19,20,21,22,23] and [28].

3. Design of the Proposed Synthesizer and Spur Analysis

3.1. Low Phase Noise PFD and CP

To operate a high-frequency phase synchronization, a true single-phase clocking (TSPC)-based PFD is implemented (Figure 8). Following the PN optimization design procedure described in [24], a small 40 ps on-time (T_L) is confirmed by simulations when 156.25 MHz input signals are locked.

Figure 9 shows the presented CP schematic with noise sources, which is the same topology described in [25]; however, BJTs are replaced by CMOS transistors. All channel current noises are included but all flicker voltage noises at the transistor (M₁–M₅) gates are omitted for simplicity. Because M_n and M_p are used for switches, their noise contributions are trivial. Most of the noises due to M₃–M₅ are filtered by R_G1–C_G1 and R_G2–C_G2 LPFs. The current noises of M₁ and M₂,

\bar{I_{M 1}^{2}} = 4 k T γ g_{m 1}

and

\bar{I_{M 2}^{2}} = 4 k T γ g_{m 2}

can be degenerated by R_dn and R_dp, respectively. However, some portions of R_dn and R_dp noises are added. Therefore, the equivalent current noise (

\bar{I_{m 1 - d g}^{2}}

) flowing through the M₁ channel is expressed as

\bar{I_{M 1 - d g}^{2}} = \frac{\bar{I_{M 1}^{2}}}{{(1 + R_{d n} g_{m 1})}^{2}} + \frac{4 k T R_{d n} {g_{m 1}}^{2}}{{(1 + R_{d n} g_{m 1})}^{2}} .

(7)

According to (7), the equivalent current noise would be close to 4kT/R_dn if R_dng_m1 is big enough. As R_dn is increased,

\bar{I_{M 1 - d g}^{2}}

is decreased. Therefore, the maximum possible R_dn must be used to minimize the equivalent current noise as long as guarantees an appropriate output tuning DC range.

To secure the degeneration R_dn benefit,

\bar{I_{M 1 - d g}^{2}}

should be less than

\bar{I_{M 1}^{2}}

, which can be expressed as

\frac{4 k T R_{d n} {g_{m 1}}^{2}}{{(1 + R_{d n} g_{m 1})}^{2} - 1} < \bar{I_{M 1}^{2}} .

(8)

When R_dng_m1 >> 1, (8) can be simplified as

\frac{1}{γ g_{m 1}} < R_{d n},

(9)

which defines the minimum required degeneration resistance to reduce the CP output noise due to

\bar{I_{M 1}^{2}}

Moreover, the flicker noises of M₁ and M₂,

\bar{V_{M 1}^{2}}

and

\bar{V_{M 2}^{2}}

, can be individually alleviated by g_m1R_dn and g_m2R_dp. Consequently, the equivalent output current noise,

\bar{I_{n c}^{2}}

, can be expressed as

\bar{I_{n c}^{2}} = \bar{I_{o t 1}^{2}} + \bar{I_{o t 2}^{2}} + \bar{I_{o f 1}^{2}} + \bar{I_{o f 2}^{2}} + \bar{I_{o r 1}^{2}} + \bar{I_{o r 2}^{2}},

(10)

where

\bar{I_{o t 1}^{2}} = \bar{I_{M 1}^{2}} {(\frac{1}{1 + g_{m 1} R_{d n}})}^{2}, \bar{I_{o t 2}^{2}} = \bar{I_{M 2}^{2}} {(\frac{1}{1 + g_{m 2} R_{d p}})}^{2}, \bar{I_{o f 1}^{2}} = \bar{V_{M 1}^{2}} {(\frac{g_{m 1}}{1 + g_{m 1} R_{d n}})}^{2}, \bar{I_{o f 2}^{2}} = \bar{V_{M 2}^{2}} {(\frac{g_{m 2}}{1 + g_{m 2} R_{d p}})}^{2}, \bar{I_{o r 1}^{2}} = \frac{4 k T R_{d n} {g_{m 1}}^{2}}{{(1 + R_{d n} g_{m 1})}^{2}} \bar{I_{o r 2}^{2}} = \frac{4 k T R_{d p} {g_{m 2}}^{2}}{{(1 + R_{d p} g_{m 2})}^{2}} .

Figure 10 shows the PN simulations of the PFD+CP when the degeneration resistance (both magnitude of R_dn and R_pn) is 62.5, 125, 250, 500, 1k, 2k, and 4k ohm. The smallest simulated PN at 1 kHz offset is –135 dBc/Hz which is 21 dB lower than that of SiT9501. However, the lowest PN at 10 kHz offset is –141dBc/Hz, which is close to that of SiT9501. Therefore, the DLL 3-dB loop bandwidth must be lower than 10 kHz to force the dominant in-band PN source for the proposed synthesizer to be the external reference clock. The best PN floor is -143 dBc/Hz.

3.2. Delay Unit

As shown in Figure 2, the VCDL is the chain of 256 DU cells. Each DU output drives DU input, but the last DU drives the inverter for a half-period lock. Therefore, to make all nodes (D₁–D₂₅₆) an identical capacitive load, the last DU should be different from the other DUs.

The DU schematic shown in Figure 11(a) is used for the first 255 DUs in the chain, which consists of two delay unit inverters (I_DUs), two varactors (V_ars), and two 3-bit C_banks. The DU output drives the multiplexer through the inverter buffer (I_B). Adding a dummy buffer inverter (I_B) at the DU_X node makes the same capacitive load for the DU_X and DU_out nodes. In addition, another dummy inverter (I_H) is applied to both DU_X and DU_out nodes, where I_H is the last DU’s load inverter for the half-period lock shown in Figure 2. Figure 11(b) shows the last DU schematic. The only difference is that the dummy inverter (I_H) is replaced by I_DU at the DU_out node. Consequently, all nodes of the DU inverter (I_DU) in the VCDL have the same capacitive load, which leads to the same delay for each DU inverter. The reason for the 3-bit C_bank is to reduce K_DL to make the DU less sensitive to the power supply and delay line noises as well as to minimize the DU PN.

The delay, D_T, from DU_in to DU_out, can be varied by adjusting the capacitance of V_ar, which is inversely proportional to the V_CT magnitude. Figure 12 shows the simulated D_T versus V_CT when two extreme process/temperature variations of FF/–20 ºC and SS/100 ºC are applied. The delay curves of FF/–20 ºC (blue) and SS/100 ºC (red) should be overlapped to overcome the variations of the ±3σ process and the −20 to 100 ˚C temperature range. The overlapped delay must include T_MS/512 to make DLL locked, which would be 12.5 ps when f_MS = 156.25 MHz. The V_CT node would converge to either 1.2 V or 0.9 V for both FF/-20 ºC/ ‘111’ C_bank state and SS/100 ºC/ ‘000’ C_bank state, respectively.

The DU chain PN simulations on DU₁₆, DU₃₂, DU₄₈, DU₆₄, and DU₈₀ outputs have been completed, as shown in Figure 13 (blue curves). Beyond the DU₈₀ output, PN simulation cannot be accomplished owing to the convergence problem in Cadence. Therefore, PN beyond the DU₈₀ output is induced by linearly expanding from the PN simulations on DU₁₆, DU₃₂, DU₄₈, DU₆₄, and DU₈₀ outputs. The average PN degradations between DU_X+16 and DU_X outputs for flicker and thermal noise regions are 1 and 0.25 dB, respectively. As a result of expansion, PN degradations of approximately 11 and 2.75 dB are estimated between DU₂₅₆ and DU₈₀ outputs (the red curve in Figure 13).

The PN contribution of S2DC (Figure 3) is trivial so the PN on P₅₁₂ is close to that on DU₂₅₆. Because V_Q or V_I in Figure 2 is continuously switched among P₁–P₅₁₂, the average PN on either V_Q or V_I is always better than that on P₅₁₂. Rather, the average PN for all possible pulses programming A₉–A1 would be close to the PN on P₁₂₈, where the estimated PN on P₁₂₈ is approximately equal to 3 dB and 0.75 dB PN degradations from the P₈₀ PN as shown in the black curve in Figure 13.

To prove the above statement, the jitter-added P₁–P₁₆ pulses on rising and falling edges are shown in Figure 14(a). The single DU’s jitter (J₁) is added on P₁. The jitter on P₂ would be double as 2J_t, and 15J_t will be accumulated finally on P₁₅. However, the jitter on P₁₆ is fixed by PFD+CP such that no jitter exists on P₁₆. For A₄–A₁ = 1, the period of V_IF is adjusted to 9t_d (the bottom in Figure 14(b)). The accumulated jitter at the rising edge of V_IF is varied as the sequence of 7J_t, 8J_t, 9J_t, 10J_t, 11J_t, 12J_t, 13J_t, 14J_t, 15J_t, 0, J_t, 2J_t, 3J_t, 4Jt, 5Jt, and 6J_t. Moreover, the accumulated jitter at the falling edge of V_IF is varied as the sequence of 11J_t, 12J_t, 13J_t, 14J_t, 15J_t, 0, J_t, 2J_t, 3J_t, 4Jt, 5Jt, 6J_t, 7J_t, 8J_t, 9J_t, and 10J_t. Therefore, the average jitter at both rising and falling edges of V_IF would be 8J_t. When A₄–A₁ = 6 (the 14t_d period waveform in Figure 14(b)), the accumulated jitter sequence at the rising edge of V_IF would be 7J_t, 13J_t, 3J_t, 9J_t, 15J_t, 5Jt, 11J_t, and J_t. The jitter sequence at the falling edge of V_IF would be 14J_t, 4J_t, 10J_t, 0, 6J_t, 12J_t, 2J_t, and 8J_t. The resulting accumulated average jitter would be 8J_t and 7J_t at the rising and falling edges of V_IF, respectively.

3.3. Programmable RFFM

As shown in Figure 2, RFFM is composed of an HG, two buffers (BUFs), and a drive amplifier (DA). The proposed HG schematic is shown in Figure 15, which has been recently published in [25,26]. [26] has implemented it as a frequency quadrupler and [25] has applied it as a programmable FM for 8–16 FMF range. The HG in this paper has been optimized for the programmable 12–32 FMF range.

All the transistors of M₁–M₆ in Figure 15 are fully turned on and off periodically by applying enough amplitude at (T_P–T_N). Figure 16(a) shows the ideal HG’s important internal voltage and current pulses. The corresponding output currents are illustrated in Figure 16(b). The delay time (T_w) between the differential signals of (T_P–T_N) and (B_P–B_N) is intentionally introduced by adjusting C_s and C_g. The current (I_M4) flows only for the duration of both T_N and B_N in the high state. Because I_M1 = I_M3 + I_M4, the high state pulse width of I_M3 is T_w but that of I_M4 is T_IF /2 – T_w, where T_IF = 1/f_IF. Similarly, I_M5 and I_M6 can be generated by applying the complementary pulses (T_P and B_P) of (T_N and B_N). The fundamental frequency of I_M3–I_M6 is still f_IN (= 1/T_IN), but their summation (I_HG⁺ and I_HG^-) fundamental frequency is 2×f_IN. Figure 16(b) shows the HG differential current (I_HG⁺ − I_HG^-) pulse (purple), which would provide strong even current harmonics.

According to (2), f_IF is equal to f_MS×(1024/1020) by programming AC_M as 254. Since f_MS is 1/(512×t_d), the corresponding period of V_IF would be 510×t_d. When t_d is 12.5-ps, the V_IF period is 6.375-ns and the period of (I_HG⁺ − I_HG^-) is 3.1875-ns. Figure 17(a) shows the 3.1875-ns fundamental period pulse with a 20-ps pulse width, 20-ps rising delay, and 20-ps falling delay. Its power spectrum is also shown in Figure 17(b). The power difference between 0.3137 and 10.04 GHz is only 2.8 dB, which means that the power is more balanced and distributed over a 0.3–10 GHz frequency band compared with a 50 % duty cycle pulse.

Unfortunately, the ideal current pulse of the above example cannot be produced because all active devices have limited bandwidth. Instead, it is more likely to draw the differential output current (I_HP⁺ − I_HP^-) as shown in Figure 17(c), which is the simulation result when AC_M is set to 254. Figure 17(d) shows the Fourier transform of (I_HP⁺ − I_HP^-). Because of the slew rate, the low-order harmonic characteristic would be expressed as highlighted with the purple dotted ellipse, which leads to more power concentration on 2×f_IF, 4×f_IF, and 6×f_IF. Consequently, the power spectrum difference between those at the lowest and the highest harmonics is now 10.2 dB, which is 7.4 dB bigger than that of the ideal (I_HP⁺ − I_HP^-) spectrum. However, the power spectrum difference between those at 1.882 and 10.04 GHz is 2.9 dB, which is only 0.2 dB bigger than that of the ideal pulse (2.7 dB power difference between those at 1.882 GHz and 10.04 GHz as shown in Figure 17(b)). As shown in Figure 15, the wanted high-order current harmonic can be conserved by programming the resonant frequency of parallel L_P and C_bank. The corresponding HRR performance would be much better than the HRR when the output current is a 50 % duty cycle pulse.

When AC_M is programmed as 253, the duration difference between the low and high states of V_IF would be t_d, as described in Figure 5(b). Consequently, the differential output current (I_HP⁺ − I_HP^-) is the sequence of 3.1875-ns and 3.175-ns periods as shown in Figure 17(e). Its spectrum appears to be close to that shown in Figure 17(d), but the noticeable adjacent harmonic happens at ±f_IF around the wanted harmonic. As shown in Figure 17(f), odd harmonics appear as 3×f_IF, 5×f_IF, ..., and 33×f_IF. The odd harmonic power is increased as frequency is increased. The worst adjacent harmonic rejection ratio (HRR) is 7.1 dB between the power levels at 10.03 and 10.187 GHz. Each DU’s delay (t_d) would be decreased as the number of DU is increased, which leads to the power spectrum reduction of odd harmonics.

The proposed HG L_P-C_bank output load schematic is shown in Figure 18(a), where M₁–M_x act as digitally controllable switches. R_LP is the equivalent parallel parasitic resistor of the inductor (L_P). The output load capacitor of summing all parasitic capacitors due to M₃–M₈ in Figure 15 and the following building block input capacitor is expressed as C_PR. The sizes of C_x and M_x are binary-weighted.

The minimum sizes of C₁ and M₁ are intentionally used to attain a wide tuning range and fine resonant frequency resolution, which results in implementing 9.64-fF C₁ and 200-nm (width)-60-nm (length) M₁ in the 65-nm CMOS technology. Figure 18(b) and Figure 18(c) show the equivalent L_P-C_bank circuitries when all M₁–M_x are turned on and off, respectively. C_S1 is the equivalent capacitance of two C₁s in series and is equal to C₁/2. However, R_S1 = 2∙R_ON1, where R_ON1 is the turn-on resistance of the M₁ switch. C_ds1 is the parasitic capacitance between the drain and the source of the turned-off M₁.

When all switches are turned off, the highest resonant frequency can be expressed as

f_{r s - m a x} = \frac{1}{2 π \sqrt{L_{P} (C_{P R} + \sum_{k = 1}^{x} C_{O F F k})}},

(11)

where

C_{O F F k} = \frac{C_{S k} C_{d s k}}{2 (C_{S k} + C_{d s k})} .

(12)

The corresponding equivalent parallel resistance would be close to R_LP.

On the contrary, the lowest resonant frequency occurs when all M₁–M_x are turned on. Therefore, it can be expressed as

f_{r s - m i n} = \frac{1}{2 π \sqrt{L_{P} (C_{P R} + \sum_{k = 1}^{x} C_{P k})}} .

(13)

C_Pk is transformed from C_Sk as the following equation:

C_{P k} = C_{S k} \frac{Q_{C}^{2}}{1 + Q_{C}^{2}}, R_{P k} = R_{S k} (1 + Q_{C}^{2}),

(14)

where Q_C = Q_S (=1/ωC_SkR_Sk) = Q_P (=ωR_PkC_Pk) and R_Pk is the transformed resistor. The corresponding equivalent parallel resistor (R_P-min) would be

R_{P - m i n} = \frac{R_{L P}}{[1 + R_{L P} \sum_{k = 1}^{x} (\frac{1}{R_{P k}})]},

(15)

which is the minimum resistance at the lowest resonant frequency.

To achieve the target output frequency band, f_rs-max in (11) should be bigger than 10 GHz but f_rs-min in (13) should be less than 2 GHz. The ratio of (11) to (13) should be greater than five and can be derived as

\frac{f_{r s - m a x}}{f_{r s - m i n}} = \sqrt{\frac{C_{P R} + \sum_{k = 1}^{x} C_{P k}}{C_{P R} + \sum_{k = 1}^{x} C_{O F F k}}} > 5 .

(16)

As C_Pk is binary weighted, that is C_P_x = 2×C_P(_x–1) = …. = 2^(x–2) ×C_P2 = 2^(x–1) C_P1, so is C_OFFk, (16) can be rewritten as

\frac{C_{P R} + {(2}^{x} - 1) C_{P 1}}{C_{P R} + {(2}^{x} - 1) C_{O F F 1}} > 25

(17)

By inserting C_PR, C_P1, and C_OFF1 as 68-fF, 4.6585-fF, 0.09675-fF (confirmed by simulations) results in 2^x > 356. Therefore, the minimum number of C_bank bits, x, is 9. Inserting x in (11) as 9 leads to 2.159-nH L_P for 10 GHz f_rs-max. By applying L_P = 2.159-nH in (13), f_rs-min becomes 2.191 GHz. Trying x = 10 in (11) to get 10 GHz (f_rs-max) results in 1.517-nH L_P. The corresponding f_rs-min is 1.859 GHz, which adheres to the initial output frequency target range of 2–10 GHz.

The AC simulations (TT-process and 25 ˚C) are shown in Figure 19(a). The impedance dB difference between the highest and lowest resonant frequencies is 26.2 dB. The red curves are simulation results when the C_bank states are “0000000000”, “0000000010”, “0000000100”, ..., and “1000000000”. The blue curves represent simulation results for programming the C_bank states from “1111100000” to “1111111111” in integer one step. The magnified curves from 1.6 GHz to 1.8 GHz are shown in Figure 19(b).

The 26.2 dB output impedance variation can be compensated by adding a negative-g_m pair (M₇–M₈ inside a Q-enhancer dotted rectangular in Figure 15). By setting KR_P = 2/g_m, the equivalent parallel impedance, R_EQ, of R_P and –2/g_m is derived [25] as

R_{E Q} = (\frac{K}{K - 1}) R_{P},

(18)

where g_m is the transconductance of M₇ and M₈. If g_m < 2/R_P and K > 1, it leads to no oscillation owing to the positive feedback pair of M₇–M₈. The tail current of the negative-g_m pair (I_Ngm in Figure 15) can be appropriately adjusted by 10-bit digital control bits such that all HG output impedances at the wanted resonant frequencies can be equalized close to 65 dBOhm.

Figure 20(a) shows process corner simulations at 27 °C. Nine different AC simulations on the HG output for SS (red), TT (black), and FF (blue) processes at the highest, amid, and lowest resonant frequencies are plotted. As expected, the impedance magnitudes at the lowest are about 26.2 ~ 30.3 dB lower than those at the highest. The impedances at the lowest and amid are equalized close to 65 dBOhm by applying I_Ngm properly as shown in Figure 20(b). The gap frequency between the lowest FF and the highest SS processes is 2–10 GHz, which might be defined as the synthesizer output frequency band overcoming ±3σ process variations.

To further improve the HRR performance of the RFFM, the HG is followed by two buffers (BUFs) whose schematic is shown in Figure 21. The BUF core is a parallel connection of a differential cascade buffer and a negative-g_m pair. The output load of L_P-C_bank is the same as that of the proposed HG. As proven in [25,26], an automatic constant amplitude control loop (ACACL) not only prevents it from oscillation but also maintains the constant output amplitude for the best performance of the following blocks. The negative-g_m pair plays the main role of the ACACL. The output amplitude is detected by a peak detector. If peak magnitude V_PK > V_R, the negative-g_m pair current is reduced to make its g_m lower. According to (18), the equivalent impedance (R_EQ) would be reduced because K is increased. Therefore, the BUF output magnitude would be decreased. On the contrary, the BUF output amplitude would be increased when V_PK < V_R. The negative-g_m pair current is varied until V_PK converges to V_R.

3.4. Adjacent HRR Simulation and Analysis

When the MASH 1-1-1 ΔΣ modulator is applied to the feedback path of a classical fractional-N PLL (CFNPLL), the CFNPLL’s total division (N) is not fixed. Instead, N keeps changing to any integer number between N-3 and N+4. The average N over a relatively long duration can be expressed as a fractional number as N + (K/M), where K and M are integers. This is the reason causing fractional spurs. In contrast, f_IF is the product of a fixed fractional number and f_MS because AC_M in (2) does not vary. Therefore, there are no fractional spurs.

Even though every I_DU output has the same capacitive load as shown in Figure 11, each DU in the VCDL might have a different delay because of a mismatch. Similar to an MDLL, any mismatch among DUs directly translates into a duty cycle error of V_IF (Figure 2). The duty cycle error causes odd harmonics in addition to even harmonics of f_IF like the spectrum shown in Figure 17(f). Therefore, the worst HRR often happens at the ± f_IF offset from the wanted harmonic.

The output L_P-C_bank loads of the HG and BUF are identical and would be expressed as a parallel of R_EQ, L_P, and C_P equivalently for all C_bank states. The corresponding HRR (dB) at ± Δω from the resonant frequency ω₀ can be derived as

{{H R R}_{\pm ∆ ω}|}_{d B} = 20 \log (R_{E Q}) + 10 \log (\frac{1}{R_{E Q}^{2}} + W^{2}),

(19)

where

W = \frac{1}{ω_{0} \pm ∆ ω} - (ω_{0} \pm ∆ ω) .

(20)

For all C_bank states, R_EQ is maintained close to 65 dBOhm by adjusting the negative-g_m pair current as shown in Figure 20(b).

As expected from (2), f_IF = 157.17 MHz when AC_M = 253. L_P-C_bank is programmed to resonate at the 12th harmonics of f_IF to distinguish 1.886 GHz (≈ 12×157.17 MHz). Recalling Figure 17(f), the dominant adjacent spurious tones of (I_HP⁺ − I_HP^-) are located at the 10th and 14th harmonics, and their HRRs of the 12th harmonic are –1.4 and 0.2 dB, respectively. Furthermore, there are noticeable spurious tones at ±f_IF offsets due to the sequence of 3.1875-ns and 3.175-ns periods of (I_HP⁺ − I_HP^-) as shown in Figure 17(e). The HRR at the 11th and the 13th harmonics of the 12th harmonic are identical and easily calculated as 13.9 dB (= −27.6 + 41.5).

The HG differential output current (I_HP⁺ − I_HP^-) is filtered by the L_P-C_bank. By simply applying ω₀ = 2π (12×157.17 MHz) in (19), the HRRs are calculated as 29.8, 23.3, 22.7, and 28.4 dB at ±2π×f_IF and ±4π×f_IF offsets. If the HG is perfectly linear, the HRRs of (H_ON – H_OP) at the 10th, 11th, 13th, and 14th harmonics should be 28.4 dB (= 29.8 – 1.4), 37.2 dB (= 23.3 + 13.9), 36.6 dB (= 22.7 + 13.9), and 28.6 dB (= 28.4 + 0.2), respectively.

Figure 22(a) shows the simulated spectrum of (I_HP⁺ − I_HP^-) along with the L_P-C_bank load impedance (red curve) resonated at the 12th harmonic of f_IF when AC_M is programmed as 253. The HG output spectrum simulation is shown in Figure 22(b). The simulated HRRs are 27.8, 36.8, 36.4, and 28.6 dB, which is degraded compared with the estimation. The HRR degradation is due to the HG nonlinearity emphasized in [26]. The simulated output harmonics of the 1st and 2nd BUFs are shown in Figure 22(c) and Figure 22(d). There are also HRR degradations due to the BUF nonlinearity.

The simulated 2nd BUF output harmonics for AC_M =127 and AC_M = 1 are individually shown in Figure 23(a) and Figure 23(b). Their f_IFs are 0.209 GHz and 0.3111 GHz, and their resonant frequencies are tuned to the 28th and 32th harmonics, respectively. Considering Figure 22(d) and Figure 23, it degrades HRR performance as the resonant frequency is increased. This is exactly the expected result because increasing C_P while maintaining R_EQ and L_P to reduce the resonant frequency results in improving the quality factor of parallel R_EQ-C_P-L_P.

4. Fabrication and Measurement

The proposed synthesizer is fabricated in a 65-nm CMOS technology and its active die size is approximately 0.6 mm² as shown in Figure 24 (yellow-dotted box). Almost 35 % of the die area is occupied by the 512-phase DLL (blue-dotted boundary), and the RFFM occupies roughly 40 % (red-dotted boundary). The last 15 % of the active die area is for the IFG (purple-dotted boundary). The total die area is 1 mm² including central reference current, SPI, IQ-offset, and I/O pads.

As described in [27], about 42 dB substrate isolation within 100-μm apart two points with only one 30-μm width guard ring is reported. Since each building block has a wider than 30-μm guard ring width in Figure 24, the substrate isolation within 100-μm apart would be expected to be more than 42 dB due to multilateral isolations. This is why we try to assign separate power supply, ground, and guard ring (GR) for each building block as much as possible even though GR occupies an extra die area.

Three separate pairs of power supply and ground are allocated for the building blocks in the 512-phase DLL. The power supply voltage is 2.5 V for the PFD+CP to obtain enough headroom. However, the power supply voltage for VCDL and the 256-S2DC is 1.2V for the smallest die area and the lowest average power consumption in the 65-nm process. There is no level shifter required between the CP and VCDL because the CP drives the DU’s varactor, whose maximum potential difference can be bigger than 2.5 V. Each pair of power supply and ground is separated by an individual GR, preventing mutual interference with one another.

The IFG has one pair of power supply and ground for its building blocks of I/Q-multiplexers and I/Q-accumulators and has wide a GR to prevent especially the reference clock harmonics (N×f_ref) from interfering.

A separate pair of 1.2 V power supply and ground is individually applied for the HG and the BUFs in the RFFM because the mutual interferences through the power supply and ground are so sensitive to the HRR performance. While the DA shares the ground with the 2nd BUF, the DA power supply is separated from the BUF power supply to distinguish the DA power consumption from that of the BUF.

The laboratory test environment is shown in Figure 25. An external MEMS differential oscillator (SiT9501) is used as a 156.25 MHz reference clock, and its integrated rms jitter from 12 kHz to 20 MHz is as low as 70.629-fs according to the datasheet. Applying a Keysight E3631A as the power supply, the fabricated chip can be evaluated by programming the CPU to control the device under test through SPI. A Keysight E4446A spectrum analyzer measures the presented synthesizer output.

The proposed synthesizer consumes 15 mW. More than 50 % of the total power consumption is allocated to the 512-phase DLL. Even though they are digital circuitries, the average power consumption of the VCDL is approximately 35 % of the total power consumption to perform low PN. However, the 256-S2DCs power consumption is 15 % because it is less sensitive to PN contribution. The power consumption of PFD+CP is 5%. The IFG and RFFM power consumptions are 1.3 and 6.2 mW, respectively. The power consumption of each building block is summarized as shown in Figure 26.

As mentioned in Section I, the proposed synthesizer is the first building block of the recent cascade LO chain for a 5G⁺ wireless communication system. Therefore, the synthesizer will drive the mmWave FM, whose impedance is normally bigger than 50 Ω. For only driving 50 Ω, a simple differential push-pull topology DA for wideband output matching is integrated. As shown in Figure 27, the DA is matched to 50 Ω through external balun (BAL-0036) and two cascade stages of the C-L-C pi-match. Figure 28(a) shows the simulation plot of the DA output (V_OUT) versus input (V_IN). The DA power gain is 9.5 dB and the output 1-dB compression point (OP1dB) is 1.6 dBm when it consumes 6 mW, which is enough to set the -8 dBm balun output without causing the significant signal distortion by the DA.

Five sample chips (Chip#1–Chip#5) have been mounted on a PCB by chip-on-board and successfully tested for evaluating performances. The DA output is placed as close to the PCB pad as possible so that the bonding wire inductor (0.35 nH L_BW in Figure 27) would be the smallest. Figure 28(b) shows the S22 measurements of the sample chips, whose worst S22 is less than −10 dB for the target measurement frequency band of 1.8–10 GHz.

The C_bank magnitude of programming the resonant frequency would be shifted over the process variation. Therefore, the auto-calibration of C_bank is required to promote an efficient mass production yield. Figure 29 shows the proposed calibration block diagram. As soon as calibration starts, all building blocks are turned off, except those highlighted in the shaded boxes of the digital 256-FD, digital 4096-FD, CMOS differential-to-single (D2S), and the negative-g_m pair of the second BUF. Applying enough current of I_ng forces the positive feedback to oscillate, and its frequency, f_osc, can be expressed as

f_{o s c} = \frac{1}{2 π \sqrt{L_{P} {(C}_{P} + C_{p a})}},

(21)

where C_pa is the all-parasitic capacitance between v_p and v_n. C_P is expressed as

C_{P} = \sum_{k = 1}^{10} (D_{k} C_{P k} + \bar{D_{k}} C_{O F F k}) .

(22)

D_k and

\bar{D_{k}}

are complement binary bits. C_OFFk and C_Pk are defined in (12) and (14). f_osc is down-converted to CK_B by 4096-FD and 2048-FD, and the external MEMS frequency, f_MS, is down-converted to CK_MS by 256-FD. The counter output in the CPU is updated at the CK_MS rate for the CK_B period. The final counted value, Cal_1-12, for each C_bank state is stored in a look-up table.

Unfortunately, the CMOS D2S would be a complicated topology to handle the wide frequency band of 1.8–10 GHz, which leads to a huge die area. Therefore, the calibrated frequency band is limited up to 2.2 GHz to minimize the D2S die area.

Table 1 shows the calibrated Cal₁₂-Cal₁ magnitudes in decimals (Cal_dec) when the C_bank states are intentionally set to oscillate at approximately 2.0, 2.05, 2.10, 2.15, and 2.20 GHz for Chip#1. The oscillation frequency can be estimated from the calibrated Cal_dec as

f_{c - o s c} = \frac{(2048) (4096)}{(256) {C a l}_{d e c}} f_{M S} .

(23)

Figure 30 shows the graph of the frequency difference (Δf_osc) between measured (f_osc) and calibrated (f_c-osc) frequencies versus f_osc for all five test chips. The maximum frequency deviation is less than 0.2 % (= 2MHz / 2GHz × 100%), meaning all the tested five chips have an approximately equal C_bank value.

Assuming that the L_P-process variation is trivial and that all capacitances are changed linearly in the same direction over process variations, (21) can be rewritten as

f_{c - o s c} = \frac{1}{2 π \sqrt{L_{P} α_{C} {(C}_{P - T T} + C_{p a - T T})}} .

(24)

The capacitive process coefficient

(α_{C}

) can be calculated by deriving (24) as

α_{C} = \frac{1}{4 π^{2} f_{c - o s c}^{2} L_{P} (C_{P - T T} + C_{p a - T T})},

(25)

where C_P-TT and C_p_a-TT are the capacitances at the TT process. Therefore, α_C represents how much the capacitance deviates from that at the TT process. If α_C is bigger than 1.2, the tested chip is close to the SS process. On the contrary, it is close to the FF process if α_C is smaller than 0.8. Using α_C the required SPI C_bank state of the resonant frequency greater than 2.2 GHz can be estimated.

The output spectral measurements for Chip#1, when AC_M is programmed as 1, 2, 127, 128, 253, and 254, are shown in Figure 31. The output frequency range is 1.882–9.961 GHz, which is close to the simulated range of the TT process.

The worst adjacent HRRs happen when AC_M = 1 (Figure 31(a)) and AC_M = 2 (Figure 31(b)) resonating with the L_P-C_bank on the 32nd harmonic of f_IF. Unlike the HRR for AC_M = 1, the dominant HRR when AC_M = 2 happens at ±2×f_IF because the duty cycle offset of V_IF is zero. Nonetheless, there are noticeable spurious tones at ±f_IF from the wanted harmonic. The main cause of these spurious tones is the HG differential mismatches. Intentionally introducing the current mismatch between the positive and negative paths of the HG might reduce the HG differential mismatch, but the detailed schematic and analysis are omitted in this article.

The proposed synthesizer output spectra resonating the L_P-C_bank on the 28th and 12th harmonics when AC_M = 127 and AC_M = 253 are shown in Figure 31(c) and Figure 31(e), respectively. As expressed in (2), f_IF decreases as AC_M increases. The adjacent offset frequencies are 208.877 and 157.171 MHz for AC_M = 127 and AC_M = 253, respectively. The corresponding output frequencies are 5.848 GHz (= 28×208.877 MHz) and 1.886 GHz (= 12×157.171 MHz). For AC_M = 128 and AC_M = 254, the HRRs at ±f_IF are better compared with the HRRs for AC_M = 127 and AC_M = 253 as shown in Figure 31(d) and Figure 31(f).

Figure 32 (a) and Figure 32(b) show all the measured worst HRRs of the sampled chips for AC_M = 1, 127, and 253 and AC_M = 2, 128, and 254, respectively. The HRR performance tendency is maintained as explained in the previous section, which leads to the HRR at a lower resonant frequency being better than that at a higher one. However, all the measured HRRs are slightly deteriorated compared with those from HRR simulations. These HRR gaps are considered owing to all the harmonics of the fundamental tone coupled to the synthesizer output through the same substrate in addition to the HG differential mismatch.

The synthesizer PN measurements (PN_SYN-1 and PN_SYN-253) are shown in Figure 33 for AC_M = 1 and AC_M = 253, with corresponding FMFs between f_MS and f_RF of 63.751 (=9.96/0.15625) and 12.071 (=1.89/0.15625). All the dotted curves are simulated PNs. The measured MEMS oscillator PN (PN_MS) is drawn to distinguish the PN degradation between f_MS and f_ref. The integrated rms jitter of f_MS from 12 kHz to 20 MHz is 72 fs, which is 1.4 fs degraded compared with the jitter in the SiT9501 datasheet.

When AC_M = 1, the estimated synthesizer PN (PN_EST-1) is simply the multiplication of FMF² and PN_SUM. PN_SUM = PN_MS + PN_LPH_l²(s) + PN_HP×H_h²(s), where H₁(s) and H_h(s) are LPF and HPF NTFs as defined in (6). Also, PN_LP is the PN simulation of PFD+CP (Figure 10), and PN_HP is the PN simulation of DU₁₂₈ shown in Figure 13. Since PN_LP is bigger than PN_HP, the 3-dB DLL loop bandwidth is set low enough for optimizing the synthesizer rms jitter from 12 kHz to 20 MHz. PN_SYN-1 green curve is PN measurement when the DLL 3-dB bandwidth is 100 Hz.

As shown in Figure 33, the estimated PN (PN_EST-1) is close to the measured PN (PN_SYN-1), proving that the most dominant noise sources are PFD+CP and VCDL. Moreover, the PN differences between PN_SYN-1 and PN_MS are approximately 39 and 38 dB at 12 kHz and 20 MHz offsets, respectively, which are only 3 and 2 dB bigger than the mathematical PN degradation due to frequency multiplication between f_RF and f_MS. The PN difference between PN_SYN-1 and PN_SYN-253 is 15 dB, close to the mathematical PN degradation (20 log (9.96/1.886)). The measured rms jitters of PN_SYN-1 and PN_SYN-253 integrated from 12 kHz to 20 MHz are 82.65 and 82.72 fs, which is a jitter degradation of approximately 10.7 fs compared with the measured integrated jitter of PN_MS (72 fs). In other words, more than 87 % of the presented synthesizer’s rms jitter comes from the reference clock. Table 2 shows the rms jitter measurements of 12k-20MHz for all five test chips. Also, the rms integrated for 1k-100MHz have been measured, and which average rms jitters are 107.606 and 107.634 fs at 1.89 and 9.96 GHz, respectively. The jitter degradation is only 9.2 fs compared with the integrated PN_MS (98.0 fs) of 1k-100MHz.

5. Summary and Conclusion

To achieve the stringent jitter performance of a beyond 5G LO generator, the cascade structures of a low-frequency synthesizer and FM have been actively researched in the recent decade. If an mmWave FM is noiseless, the FM output jitter equals the lower synthesizer jitter. Therefore, the lower-frequency synthesizer integrated rms jitter must be less than the LO generator target specification. Otherwise, without a PN filter function, the FM output integrated rms jitter cannot achieve the jitter specification.

ILPLL and SSPLL have been successfully developed for the lower-frequency synthesizer to enhance in-band PN by removing the frequency divider in the feedback path. However, VCO jitters in both ILPLL and SSPLL are still accumulated over the injection and subsampling clock periods. Therefore, the output PNs are degraded enough to affect the integrated rms jitter performance, particularly for a wide integrated frequency band. Moreover, their channel resolutions and frequency ranges are poorer than those of the classical Integer-N PLL (CINPLL). In addition, they normally require extra circuitries to program the output frequency and prevent them from losing lock states.

In this article, a new DLL-based synthesizer topology is introduced. The 512 phases (P₁-P₅₁₂) are equally spaced by a 512-phase DLL (Figure 2). The I/Q multiplexer outputs (V_I and V_Q) are initially connected to P_I and P_Q. Next, V_I and V_Q switched to P_I±ACM and P_Q±ACM, where AC_M is the programmable input magnitude of the I/Q accumulator. As keeping switch by AC_M, the period of V_I and V_Q would be (512 ± 2AC_M)×t_d, where t_d = T_MS/512. Therefore, the fundamental frequency (f_IF) of the XOR output (V_IF) can be derived as (2).

If V_I and V_Q switch only to the phase lag signal, equation (2) can be rewritten as

f_{I F} = f_{M S} (\frac{1024}{512 + 2 {A C}_{M}}) = f_{M S} (1 + \frac{512 - 2 {A C}_{M}}{512 + 2 {A C}_{M}}) .

(26)

Equation (26) shows that f_IF can be programmed as a fractional multiple of f_MS (= f_ref) similar to CFNPLL output frequency, f_CFN, as

f_{C F N} = f_{r e f} (N + \frac{K}{M}),

(27)

where K and M are integers. And, its channel resolution is f_ref / M which is normally smaller than the proposed synthesizer channel resolution defined in (4). On the contrary, the proposed synthesizer provides a finer channel resolution than ILPLL, SSPLL, and CINPLL by setting

{R F}_{F M F} \frac{512 - 2 {A C}_{M}}{512 + 2 {A C}_{M}} < 1 .

(28)

Normally, a CFNPLL provides fractional spurs close to an output frequency, which degrades integrated jitter somewhat. In addition, the ΔΣ modulator in the feedback path of CFNPLL contributes a quite bit of integrated jitter. However, the proposed synthesizer removes the above-mentioned penalties for fractional multiplication due to the fixed fractional multiplication.

Recently, injection-locked frequency multipliers (ILFMs) have proven to be an efficient topology for unwanted harmonic suppression. However, ILFMs suffer from a narrow injection-locked frequency range. Moreover, they may require additional circuitries to maintain the lock state, particularly for high-order harmonic injections.

The synthesizer implemented in this paper has the same FM topology as the one reported in [26], but the presented FM is optimized to achieve the maximum frequency range using the smallest switch and capacitor sizes. The output resonant frequency is tuned by varying the C_bank magnitude while keeping the same parallel inductor (L_P) and equivalent resistance (R_EQ). Therefore, the highest quality factor (Q) of the L_P-C_bank load can be achieved at the lowest resonant frequency because Q is proportional to the square root of the total capacitance magnitude. Consequently, the HRR performance is degraded as the wanted frequency is increased.

Table 3 shows the specification comparison of state-of-the-art synthesizers with the proposed synthesizer. While [23] and [28] provide the rms jitter integrated from 10 kHz to 30 MHz, the other references including this work have measured rms jitter integrated from 1 kHz to 100 MHz. The active die area of [19] and [21] is the smallest (0.2 mm²). Synthesizers proposed in [19] and [22] consume a relatively low power. The jitter performance of [21] is only 58.2 fs, which is the smallest. The synthesizer proposed in [28] provides the widest frequency bandwidth.

For fair performance comparison, two figure-of-merits (FoMs) are introduced. FoM₁ and FoM₂ are defined at the bottom of Table 3. FoM₁ includes integrated rms jitter and power consumption, which are used for all the references. FoM₂ is added to include frequency bandwidth percentage in the comparison metric. As a result, the synthesizer implemented in [19] accomplishes the best FoM₁. Still, this work achieves the best FoM₂, which might mean the proposed synthesizer performs outstanding overall compared with the other state-of-the-art synthesizers.

Author Contributions

Conceptualization, K.N., N.H. and J.P.; methodology, K.N., N.H. and J.P.; validation, K.N. and N.H.; formal analysis, K.N. and J.P.; investigation, K.N., N.H. and J.P.; data curation, K.N. and N.H.; writing—original draft preparation, K.N., N.H. and J.P.; visualization, K.N. and N.H.; supervision, J.P.; project administration, J.P.; funding acquisition, J.P. All authors have read and agreed to the published version of the manuscript.

Funding

Please add: This research was supported by Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korea government (MSIT) (No.2020-0-00216, Development of mmWave data conversion free Phased-Array Tx based on 6PMP).

Data Availability Statement

Data are contained within the article.

Acknowledgments

The Eda tool was supported by the IC Design Education Center (IDEC), Korea.

Conflicts of Interest

The authors declare no conflicts of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.

References

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Figure 1. Block diagrams: (a) MDLL; (b) SSPLL; (c) ILPLL.

Figure 2. The proposed synthesizer block diagram.

Figure 3. 256-S2DCs (a) Schematic. (b) Output waveforms.

Figure 4. (a) P₁-P₁₆, V_Q and V_I (18t_d period), and V_Q (4t_d period) pulses. (b) V_Q, V_I, and V_IF pulses when AC_M = 2-6 and switching to phase lag. (c) V_Q, V_I, and V_IF pulses when AC_M = 1-5 and switching to phase lead.

Figure 5. V_IF, V_I, and V_Q waveforms. (a) V_IF is 50% duty cycle. (b) V_IF are ±0.5t_d duty cycle offsets from the 50 % duty cycle.

Figure 6. Phase noise sources of the proposed synthesizer.

Figure 7. Clock waveforms of (a) Ideal reference. (b) Jitter accumulated VCO.

Figure 8. TSPC PFD schematic.

Figure 9. Charge pump schematic.

Figure 10. The proposed PFD+CP PN simulations increase R_dn and R_dp as 62.5, 125, 250, 500, 1000, 2000, and 4000 Ω.

Figure 11. Proposed schematic. (a) The first 255 DUs. (b) The last DU in the VCDL DU chain.

Figure 12. DU SS/100ºC and FF/−20ºC simulation.

Figure 13. PN simulations on DU₁₆, DU₃₂, DU₄₈, DU₆₄, and DU₈₀ (blue curves) and estimated PN curve (red) on DU₂₅₆.

Figure 14. (a) Jitter added P₁-P₁₆ waveforms. (b) Jitter added V_PSP V_PSN, and V_XOR pulses for 14t_d (top) and 9t_d (bottom).

Figure 15. Harmonic generator schematic.

Figure 16. Proposed HG ideal. (a) Internal voltage and current pulses. (b) Single and differential output current pulses.

Figure 17. Ideal (I_HG⁺ − I_HG^-). (a) Pulse. (b) Spectrum. For AC_M = 254, simulated (I_HG⁺ − I_HG^-). (c) Pulse. (d) Spectrum. For AC_M = 253, simulated (I_HG⁺ − I_HG^-). (e) Pulse. (f) Spectrum.

Figure 18. (a) HG output L_P-C_bank. (b) Equivalent parallel L_P-C_bank. (b) When all M₁–M₁₀ are turned on. (c) When all M₁-M₁₀ are turned off.

Figure 19. HG differential output (H_OP – H_ON) impedance simulations. (a) TT process at 25°C. (b) Zoomed simulations.

Figure 20. HG differential output (H_OP – H_ON) AC simulation for FF, TT, and SS processes. (a) Without negative-g_m. (b) With negative-g_m compensation.

Figure 21. Schematic of a buffer with an ACACL.

Figure 22. For AC_M = 253. (a) (I_HG⁺ − I_HG^-) spectrum. (b) HG output spectrum. (c) First BUF output spectrum. (d) Second BUF output spectrum.

Figure 23. The second BUF output spectrum. (a) AC_M = 127. (b) AC_M = 1.

Figure 24. Photograph of the proposed synthesizer.

Figure 25. Test environment block diagram.

Figure 26. Test environment block diagram.

Figure 27. Driver amplifier with external output matching.

Figure 28. DA. (a) OP1dB simulation. (b) S22 measurements of chip#1 ~ chip#5.

Figure 29. Capacitor bank (C_bank) calibration block diagram.

Figure 30. Oscillating frequency calibration error.

Figure 31. The synthesizer output spectrum waveform. (a) AC_M =1 and RF_FMF =32. (b) AC_M =2 and RF_FMF =32. (c) AC_M =127 and RF_FMF =28. (d) AC_M =128 and RF_FMF =28. (e) AC_M =253 and RF_FMF =12. (f) AC_M =254 and RF_FMF =12.

Figure 32. The synthesizer output worst HRRs. (a) AC_M = 1, 127, and 253. (b) AC_M = 2, 128, and 254.

Figure 33. The synthesizer PN curves of 1.89 and 9.96 GHz.

Table 1. Counter Output.

C_bank D₁₀-D₁	Cal₁₂-Cal₁ Magnitude in decimal (Cal_dec)
C_bank D₁₀-D₁	Chip#1	Chip#2	Chip#3	Chip#4	Chip#5
1101010101	2561	2562	2561	2560	2560
1100101011	2499	2498	2499	2499	2499
1100000101	2400	2400	2439	2438	2439
1011100001	2382	2383	2382	2382	2383
1011000000	2328	2328	2328	2329	2327

Table 2. RMS jitter measurement.

	Chip#1	Chip#2	Chip#3	Chip#4	Chip#5
RMS Jitter [fs] @ 1.89 [GHz]	82.65¹	83.12¹	82.14¹	81.84¹	83.74¹
RMS Jitter [fs] @ 1.89 [GHz]	107.6²	107.9²	107.43²	107.12²	107.98²
RMS Jitter [fs] @ 9.96 [GHz]	82.72¹	83.54¹	82.34¹	82.21¹	84.13¹
RMS Jitter [fs] @ 9.96 [GHz]	107.57²	107.83²	107.48²	107.24²	108.05²

¹ Integrated from 12k to 20M. ² Integrated from 1k to 100M.

Table 3. Comparison with state-of-the-art synthesizer.

Parameter	[19]	[20]	[21]	[22]	[23]	[28]	This work
Tech.	65mm CMOS	28mm CMOS	28mm CMOS	65mm CMOS	65mm CMOS	65mm CMOS	65mm CMOS
f_ref [MHz]	50.0	125.0	500.0	150.0	200.0	10	156.3
f_out [GHz]	12–14.5	18.9–22.3	11.9–14.1	3–3.7	24–28.2	0.1–5	1.88–9.96
Frequency Bandwidth [%]	18.9	16.5	16.9	20.9	16.1	192.2	136.5
rms jitter [fs]	83.0 (1k-100M)	71.8 (1k-100M)	58.2 (1k-100M)	135.0 (1k-100M)	65.4 (10k-30M)	960¹ (10k-30M)	107.6 (1k-100M)
Active Die area [mm²]	0.2	0.5	0.2	0.4	0.5	1.44	0.6
Power consumption [mW]	7.7	36.0	18.0	9.5	14.5	21	17.0
FoM₁²	-252.8	-247.3	-252.1	-247.6	-252.1	-227.1	-246.9
FoM₂³	-265.5	-259.5	-264.4	-260.8	-264.1	-250.0	-268.25

¹ Referred from phase noise plot. ²

{F o M}_{1} = 20 \log (r m s j i t t e r) + 10 \log (p o w e r c o n s u m p t i o n) .

{F o M}_{2} = {F o M}_{1} - 10 \log (\frac{F W}{1 %}) .

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A Cascade Fractional-N Synthesizer Topology of DLL and Frequency Multiplier for 5G+ Communication Systems

Abstract

1. Introduction

2. Topology, Analysis, And Frequency Range

2.1. Synthesizer Topology, RF Range, and Channel Resolution

2.2. Phase Noise Analysis and no Jitter Accumulation

3. Design of the Proposed Synthesizer and Spur Analysis

3.1. Low Phase Noise PFD and CP

3.2. Delay Unit

3.3. Programmable RFFM

3.4. Adjacent HRR Simulation and Analysis

4. Fabrication and Measurement

5. Summary and Conclusion

Author Contributions

Funding

Data Availability Statement

Acknowledgments

Conflicts of Interest

References

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