preprints.org > engineering > electrical and electronic engineering > doi: 10.20944/preprints202410.0173.v1 (registering DOI)

Preprint Article Version 1 This version is not peer-reviewed

Version 1 : Received: 2 October 2024 / Approved: 2 October 2024 / Online: 2 October 2024 (13:10:31 CEST)

This study presents a synthesizer topology based on a DLL and programmable frequency multiplier for 5G+ communication systems. The proposed synthesizer comprises a 512-phase DLL, an intermediate frequency generator (IFG), and an RF frequency multiplier (RFFM). The 512-phase DLL provides 512 delayed pulses through a chain of 256 delay units and single-to-differential complementary converters (S2DCs). The IFG comprises I/Q-multiplexers, I/Q-accumulators, an XOR, and an S2DC. The I/Q-multiplexer outputs switch to the phase lag or lead waveforms at every rising or falling edge of the outputs, which makes the I/Q-multiplexer output frequency, fMX, programmable. The IF, fIF, is two times fMX, and fIF is up-converted to RF, fRF, through the RFFM. When reference clock frequency, fref is 156.25 MHz, the fIF range is 156.863–312.5 MHz and the fRF dynamic range is approximately 1.89–9.96 GHz. The channel resolution range is 3.698–38.609 MHz. Consequently, the proposed synthesizer provides a wide 134 % output frequency bandwidth and a finer channel resolution smaller than fref. The presented synthesizer is fabricated in a 65-nm CMOS process. The total power consumption is 15 mW, and the rms jitter integrated from 12 kHz to 20 MHz measured as 83 fs.

5G synthesizer; CMOS integrated circuits; delay-locked loop (DLL); harmonic suppression; integrated rms jitter; programmable frequency multiplier; phase locked loop (PLL)

Engineering, Electrical and Electronic Engineering

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