Dynamic power reduction in SRAM (Static Random Access Memory) is essential for improving energy efficiency in modern digital systems, especially in processors and embedded devices. As SRAM power consumption contributes significantly to overall chip power, optimizing power in SRAM is critical. This thesis explores recent techniques for dynamic power reduction in SRAM, with a focus on architectural modifications, dynamic voltage scaling, adaptive voltage supply, and optimized circuit designs. This abstract outlines the need for low-power SRAM in reducing heat, noise, and electro-migration, particularly in high-performance computing. The research highlights how Multi-Tree Voltage Regulator (MTR) techniques and other dynamic power management methods contribute to significant reductions in power and heat generation, thereby enhancing both performance and reliability.