ARTICLE
|
doi:10.20944/preprints202410.0173.v1
Subject:
Engineering,
Electrical And Electronic Engineering
Keywords:
5G synthesizer; CMOS integrated circuits; delay-locked loop (DLL); harmonic suppression; integrated rms jitter; programmable frequency multiplier; phase locked loop (PLL)
Online: 2 October 2024 (13:10:31 CEST)