Microwave Power Modules (MPM) are high power devices largely used for radar applications. An MPM is a hybrid combination of a Solid-State Power Amplifier (SSPA) as a driver and a Traveling wave tube amplifier (TWT) as the final high power stage. Power equalizer is often used to flat the TWT output power gain owing to its big gain fluctuations in the operating frequency range. This paper deals with an optimal design and development of a fully-coaxial easy-tunable power equalizer for an X-band MPM. The structure utilizes a coaxial waveguide as the main transmission line and a coaxial cavity loaded with absorbing material as the resonant unit. A sensitivity analysis of the coaxial cavity length, the thickness of the absorbing disc and inserted depth of the probe on the attenuation amplitude and resonant frequency is carried out. The transmission characteristic curves and the voltage standing wave ratio curves show a good compromise in terms of transferred power and adaptive matching impedance at the input and output ports. The measured results show that the equalization curve meets the requirements well and prove that this structure is practical and effective.

Low dropout (LDO) regulators are widely used in portable electronic devices because they 1 occupy small chip and printed circuit board (PCB) areas. This work presents the design of a low 2 noise low dropout (LDO) linear voltage regulator using folded cascode operational amplifier and 3 source follower buffer for frequency compensation. The proposed design achieves low output noise 4 with feedback loops, which makes it possible to improve load and line regulations as well as the 5 transient response for voltage applications in comparison with the literature. The designed LDO 6 linear regulator works under the input voltage of 2.8-4.8 V and provides up to 100 mA load current 7 for an output voltage of 2.6 V. 8 9 Moreover, the operational amplifier design contributes to the major reduction in the frequency 10 noise, and make sure the stability of LDO under different conditions. Furthermore, the novel LDO 11 design topology has very less dropout voltage, fast transient response and minimized power dissi- 12 pation under maximum load current, worst process corner, and maximum temperature to achieve 13 high power efficiency, maintain output voltage in the presence of fast load changes, and to lower the 14 power loss across the pass element especially at high load. Design criteria are addressed in detail. 15 16 This LDO topology is able to achieve ultra-low noise i.e. 2 /muv/√Hz for frequency >1kHz. The 17 proposed LDO is implemented in the cadence virtuoso H9A with CMOS 130 μm technology