This paper details the approach to the efficient design and optimization of reversible adder and multiplier utilizing Peres gates which is a three input, three output gate. Peres gates are recognized for their universality and energy efficient properties and present an intriguing option for constructing reversible circuits. Reversible logic are characterized by its ability to uniquely determine input states from output states. The design methodology involves a cascading arrangement of Peres gates each performing a reversible XOR operation on corresponding bits of the input numbers and the carry out from the preceding stage. The paper presents a detailed schematic representation, simulation results and analysis of the proposed designs of different adders and multipliers showcasing their potential for reversible applications. The integration of Peres gates in the adder and multiplier design signifies a step forward in the exploration of reversible logic circuits and their applications in contemporary computing paradigms. The overall hardware reduction is the main achievement of this research in terms of quantum cost.

Convolution forms one of the most essential operations for the FPGA-based hardware accelerator. However, the existing designs often neglect the inherent architecture of FPGA, which puts forward an austere challenge on hardware resource requirements. Even though some previous works have proposed approximate multipliers or convolution acceleration algorithms to deal with this issue, the inevitable accuracy loss and resource occupation easily lead to performance degradation. Toward this, we first propose two kinds of resource-efficient optimized accurate multipliers based on LUTs or carry chains. Then targeting FPGA-based platforms, a generic multiply-accumulate structure is constructed by directly accumulating the partial products produced by our proposed optimized radix-4 Booth multipliers without intermediate multiplication and addition results. Experimental results demonstrate that our proposed multiplier achieves a maximum 51% look-up-table (LUT) reduction compared to the Vivado area optimized multiplier IP. Furthermore, the convolutional process unit using the proposed structure achieves a 36% LUT reduction compared to existing methods. As case studies, the proposed method is applied to DCT transformer and LeNet to achieves hardware resource saving without loss of accuracy.

Conceal carry weapon (CCW) laws have generated a great deal of public discussion in the past decades, but little social science attention. Scholarly worked on the topic has been focused on finding potential effects of such laws on crime and victimization; little has attempted to explain the trends behind the adoption of the laws. This paper attempts to fill that gap by testing a series of hypotheses grounded in minority threat approaches. Our paper examines whether or not changes in the racial and ethnic composition of a county predict the voting outcome of Missouri’s 1999 conceal-carry referendum. Findings fail to reject the null hypothesis and show the best predictor of the vote within a county was how that county voted in the 2000 Presidential election.