Resilience has been defined as one's competence to maintain a mental health state and overall well-being when undergoing grave stress or facing significant adversities. Numerous resili-ence-investigating research tools were developed over the years, with the Connor-Davidson Re-silience Scale (CD-RISC), a self-rated tool presenting valuable psychometric properties, remaining one of the most prominent. We aimed to translate and validate the brief CD-RISC-10 in a convenient sample of 584 nurses in Greece's secondary and tertiary health care system. We conducted a con-firmatory factor analysis and known-groups validity and estimated the reliability of the CD-RISC-10. Our confirmatory factor analysis revealed that the scale had a unifactorial structure since all the model fit indices were very good. Moreover, the reliability of the CD-RISC-10 was very good since Cronbach's alpha was 0.924 and McDonald's omega was 0.925. Therefore, the Greek version of the CD-RISC-10 confirmed the factor structure of the original one and had very good validity and reliability.

Transactivation Response Element RNA-binding Protein (TRBP) is a double-stranded RNA-binding protein widely known for its critical contribution to RNA interference (RNAi), a conserved mechanism of gene-expression regulation mediated through small non-coding RNA moieties (ncRNAs). Nevertheless, TRBP has proved to be also involved in other molecular pathways and biological processes, such as cell growth, organism development, spermatogenesis and stress response. Mutations or aberrant expression of TRBP have been previously associated with diverse human pathologies, including Alzheimer’s disease, Cardiomyopathy and Cancer, with TRBP playing essential role(s) in proliferation, invasion and metastasis of tumor cells. Hence, the present study aims to investigate new, still elusive, functions and properties of TRBP, particularly regarding its cell cycle-dependent regulation during cancer-cell division. Our results unveil, for the first time, the tight and remarkable, mitosis-dependent, control of TRBP protein expression, as clearly evidenced by the lack of its immunofluorescence-facilitated detection, during mitotic phases, in several human cancer-cell lines of different tissue origin. Notably, the obtained TRBP-downregulation patterns seem to derive from molecular mechanisms that act independently of oncogenic activities (e.g., malignancy grade), metastatic capacities (e.g., low versus high) and mutational signatures (e.g., p53-/- or p53ΔΥ126) of cancer cells. Taken together, we, herein, propose that TRBP serves as a novel cell cycle-dependent regulator, likely exerting mitosis-suppression functions, and, thus, its mitosis-specific downregulation can hold strong promise to be exploited for the efficient and successful prognosis, diagnosis and (radio-/chemo-)therapy of diverse human malignancies, in the clinic.

The advantage of FPGAs lies in the ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small "soft-core" processor implementing I/O in software. With the goal to design and evaluate a new tiny soft-core processor optimized for FPGA resources in I/O , a novel processor named Baby8 is developed. It is an 8-bit CISC soft-core processor optimized for reduced FPGA resources including program size for 8-bit applications. The number of instructions is not large but any instruction can access arbitrary memory locations. The performance and resource utilization of the newly designed processor are evaluated and compared with a variety of other soft-core processors. The results demonstrate its competitive performance, achieving an average maximum clock frequency of approximately 57 MHz and a power consumption of around 2mW. Furthermore, it conserves nearly half of the FPGA resources in implementation.

RISC-V offers a modular technical approach combined with an open, royalty-free instruction set architecture (ISA). This openness allows various researches to incorporate RISC-V into both open and proprietary solutions or services. However, despite its advantages as a fundamental building block for many embedded systems, the escalating complexity and functional demands of real-time applications have made adhering to response time deadlines challenging. This has led to an increased demand for comprehensive development insights for real-time systems based on RISC-V. To improve development efficiency, we offer a detailed performance analysis of RISC-V in comparison to various ISAs. In this paper, we analyze the real-time performance of RISC-V through two real-time approaches based on processor architectures. For RTOS applications, we adopted FreeRTOS and evaluated its performance on HiFive1 Rev B (RISC-V) and STM3240G-EVAL (ARM M) to evaluate real-time performance. For Real-time Linux, we utilized Linux with the Preempt-RT patch and tested its performance on VisionFive 2 (RISC-V), MIO5272 (x86-64), and Raspberry Pi 4 B (ARM A). Through these experiments, we examined the real-time mechanism of each operating system. Additionally, in the Preempt-RT experiments, scheduling latencies were evaluated using cyclictest. Finally, in order to practically show the real-time capabilities of RISC-V, we implemented motion control of a six-axis collaborative robot, which was performed on the VisionFive 2 platform. This implementation provided a comparative result of RISC-V’s performance against the x86-64 architecture of MIO-5272. Ultimately, the results indicated that the real-time performance of RISC-V for real-time applications was slightly inferior to that of the x86-64 architecture. A noticeable achievement of this research was the first implementation of an EtherCAT Master on RISC-V designed for real-time applications featuring a multi-tasking structure. The research offers valuable insights into the real-time capabilities of RISC-V compared to established architectures like x86-64. While RISC-V might not surpass these architectures in real-time performance, its flexibility, modularity, and open nature make it a compelling choice for a wide range of real-time applications. The successful implementation of the EtherCAT Master on RISC-V further expands its potential in the domain of real-time embedded control systems.

In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and it is important to evaluate their performance in specific use cases. This paper evaluates the energy consumption and resource utilization of a new RISC-V processor, RisCO2, and four existing processors - Zero-riscy, Micro-riscy, Ri5cy, and CV32E40P - in a signal demodulation application for NDIR CO2 sensors. The processors were implemented in the PULPino SoC and synthesized using Vivado IDE. The processor named RisCO2 is based on the RV32E_Zfinx instruction set and was designed from scratch by the authors specifically for low-power signal processing applications such as signal demodulation in CO2 NDIR sensors. The other processors are Ri5cy, Micro-riscy, and Zero-riscy, developed by the PULP Platform team, and CV32E40P (derived from Ri5cy) from the OpenHW Group, all of them widely used in the RISC-V community. Our experiments showed that RisCO2 had the lowest energy consumption among the five processors, with a 53.5% reduction in energy consumption compared to CV32E40P and a 94.8% reduction compared to Micro-riscy. Additionally, RisCO2 had the lowest FPGA resource utilization compared to the best-performing processors, CV32E40P and Ri5cy, with a 46.1% and a 59% reduction in LUTs, respectively. Our findings suggest that RisCO2 is a highly energy-efficient RISC-V processor for NDIR CO2 sensors that require signal demodulation. The results also highlight the importance of evaluating processors in specific use cases to identify the most energy-efficient option. This paper provides valuable insights for designers of energy-efficient embedded systems using RISC-V processors.