The implementation of Boolean functions using Nano crossbar- based switching lattices has been suggested as a substitute for conventional CMOS-based approaches in digital circuits . This alternative may satisfy the needs of future electronic designs, con- sidering the expected end of Moore’s law. This study introduces CVM, a Crossbar-based circuit Verification through Modeling tech- nique

Multiply-accumulate calculations using a memristor crossbar array is an important method to realize neuromorphic computing. However, the memristor array fabrication technology is still immature, and it is difficult to fabricate large-scale arrays with high-yield, which restricts the development of memristor-based neuromorphic computing technology. Therefore, cascading small-scale arrays to achieve the neuromorphic computational ability that can be achieved by large-scale arrays, which is of great significance for promoting the application of memristor-based neuromorphic computing. To address this issue, we present a memristor-based cascaded framework with some basic computation units, several neural network processing units can be cascaded by this means to improve the processing capability of the dataset. Besides, we introduce a split method to reduce pressure of input terminal. Compared with VGGNet and GoogLeNet, the proposed cascaded framework can achieve 93.54% Fashion-MNIST accuracy under the 4.15M parameters. Extensive experiments with Ti/AlOx/TaOx/Pt we fabricated are conducted to show that the circuit simulation results can still provide a high recognition accuracy, and the recognition accuracy loss after circuit simulation can be controlled at around 0.26%.

Memristor has attracted a lot of interest due to its high processing speed, low power consumption and high integration ability, which is critical for electronic systems and memory-centric computing. However, the memristor programming circuit and strategy are still inflexible and complex, since the signal generator/collector and stimulate pulse must be carefully matched and designed based on memristor intrinsic characteristics without reconfigurable. Here, a simple and effective circuit only consists a parallel reference-resistor-and-NMOS is designed to program memristor with a more than 99% memristance precision. And the amplitude and width of stimulate pulse are fixed to ±4V and 5ms, respectively. In order to cope with the device variation, such as ±10% tolerance of transition voltage, an optimized programming strategy was proposed and demonstrated great robustness. Additionally, a set of reference resistors and NMOSs have been added to facilitate multi-level memristance operation without requiring any changes to the circuit structure. This program circuit was also employed to program memristor crossbar remains 99% precision. In the end, a memristor-based convolutional neural network which controlled by our optimized programming circuit was used for image recognition, and 89.36% accuracy can be achieved even under 15.8% memristance tolerance. This novel circuit demonstrates a simple and flexible strategy in memristor programming, providing a new way to control memristor crossbar for practical application.

In this article, we propose a circuit to imitate the behavior of a Reward-Modulated Spike-Timing-Dependent Plasticity synapse. When two neurons in adjacent layers produce spikes, each spike modifies the thickness of the common synapse. As a result, the synapse’s ability to conduct impulses is controlled, leading to an unsupervised learning rule. By introducing a reward signal, reinforcement learning is enabled by redirecting the growth and shrinkage of synapses based on signal feedback from the environment. The proposed synapse manages the convolution of the emitted spike signals to promote either the strengthening or weakening of the synapse, which is represented as the resistance value of a memristor device. As memristors have a conductance range that may differ from the available current input range of typical CMOS neuron designs, the synapse circuit can be adjusted to regulate the spike’s amplitude current to comply with the neuron. The circuit described in this work allows for the implementation of fully interconnected layers of neuron analog circuits. This is achieved by having each synapse reconform the spike signal, thus removing the burden of providing enough power from the neurons to each memristor. The synapse circuit was tested using a CMOS analog neuron described in the literature. Additionally, the article provides insight into how to properly describe the hysteresis behavior of the memristor in Verilog-A code. The testing and learning capabilities of the synapse circuit are demonstrated in simulation using the Skywater-130nm process. The article’s main goal is to provide the basic building blocks for Deep Neural Neural Networks relying on spiking neurons and memristors as the basic processing elements to handle spike generation, propagation, and synaptic plasticity.