Recent advancements in Artificial Intelligence (AI) and generative models have significantly accelerated the evolution of internet services. In data centers, where data is often distributed across multiple machines, leveraging these machines to expedite the training of machine learning applications is common. However, this approach incurs substantial communication overhead. To mitigate this, data compression techniques such as quantization, sparsification, and dimension reduction are gaining attention, especially with iterative training algorithms that frequently exchange gradients. With the advancement of FPGA technology, FPGA-based bump-in-the-wire network interface controllers (smartNICs) have demonstrated notable benefits for data centers, matching ASIC switches in port-to-port latency and capacity. However, FPGA-based switches often have spare hardware resources beyond their switching functions, which are typically wasted. we propose a novel architecture that integrates FPGA-based switches with ensemble learning methods, utilizing these spare resources on FPGA-based network switches. This architecture employs random projection as a compression method to accelerate machine learning tasks while maintaining high accuracy. Our system accelerates the training process for Multilayer Perceptron (MLP) models with a speedup of 2.1-6.7 times across four high-dimensional datasets. In addition, it leverages the Hamming distance metric for k-Nearest Neighbors (kNN) classification, combining random projection with Hamming encoding, to offload large-scale classification tasks from downstream servers. This achieves a worst-case speedup of 2.3-8.7 times and a memory reduction of 3.9-27.7 times compared to CPU-based kNN classifiers using cosine distance. Our architecture addresses the challenges of high-dimensional data processing and exemplifies the potential of AI-driven solutions in accelerating and optimizing internet services. Moreover, the programmability of FPGAs allows the system to adopt various compression methods, extending its applicability. Offloading tasks to FPGAs can significantly reduce query response times, showcasing a crucial step towards achieving greater levels of autonomic computing and the rapid evolution of internet systems.

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., Look-up tables (LUTs), flip-flops (FFs), etc. using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs are created that fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across chip routing. Data is collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

Diffuse correlation spectroscopy (DCS) is a non-invasive technology for the evaluation of the blood perfusion in deep tissue. However, it requires high computational resources for data analysis which poses challenges in its implementation for real-time applications. To address the unmet need, we developed a novel device-on-chip solution that fully integrates all the necessary computational components needed for DCS. It takes the output of a photon detector and determines the blood flow index (BFI). It is implemented on a Field Programmable Gate Array (FPGA) chip including a multi-tau correlator for the calculation of the temporal light intensity autocorrelation function and a DCS analyzer to perform the curve fitting operation that derives the BFI. The FPGA DCS system was evaluated against a lab-standard DCS system for both phantom and cuff-ischemia studies. The results indicate that the autocorrelation of the light correlation and BFI from both the FPGA DCS and the reference DCS matched well. Furthermore, the FPGA DCS system was able to achieve a measurement rate of 50 Hz and resolve pulsatile blood flow.

Edge computing helps radio-supported mobile systems to process computing tasks on the side of servers. The proximity to an edge computing node avoids excessive latencies, which benefits the calculation of real-time algorithms. Special computing needs arise because mobile systems are often so limited in weight and energy that they cannot carry powerful on-board computers. We propose the use of FPGA-based co-processors (FPGA: Field Programmable Gate Array) to handle computations in an edge node. The calculation of the Fast Fourier Transformation (FFT) will be presented as an example of a co-processor. The use of FPGA-based co-processors poses a particular challenge when a mobile system leaves its radio cell, and the computing context must be transferred to another edge node. The article first addresses specific edge computing requirements, such as case-by-case reconfiguration of computing hardware and the handover mechanism from one edge node to another. Using the example of an FPGA-based FFT co-processor, we describe its development, which was carried out under the condition that mobile clients can request different co-processors and that they can also change the edge node when changing the radio cell. The latter requires passing the co-processor context. For the FPGA, this means that the co-processor is part of a partially reconfigurable environment and must support the handover mechanisms in hardware. At the end we indicate the need for FPGA resources and compare this with alternative solutions.

This proposed research explores a novel approach to image classification by deploying a complex-valued neural network (CVNN) on a field-programmable gate array (FPGA), specifically for classifying 2D images transformed into polar form. The aim of this research is to address the limitations of existing neural network models in terms of energy and resource efficiency, by exploring the potential of FPGA-based hardware acceleration in conjunction with advanced neural network architectures like CVNNs. The methodological innovation of this research lies in the Cartesian to polar transformation of 2D images, effectively reducing the input data volume required for neural network processing. Subsequent efforts focused on constructing a CVNN model optimized for FPGA implementation, emphasizing the enhancement of computational efficiency and overall performance. The experimental findings provide empirical evidence supporting the efficacy of the image classification system developed in this study. One of the developed models, CVNN_128, achieves an accuracy of 88.3% with an inference time of just 1.6ms and a power consumption of 4.66mW for the classification of the MNIST test dataset consists of 10,000 frames. While there is a slight concession in accuracy compared to recent FPGA implementations that achieve 94.43%, our model significantly excels in classification speed and power efficiency—surpassing existing models by more than a factor of 100. In conclusion, the paper demonstrates the substantial advantages of FPGA-implementation of CVNNs for image classification tasks, particularly in scenarios where speed, resource, and power consumption are critical. The study’s reproducible results and corresponding code are available on GitHub at the following link: https://github.com/mahmad2005/CVNNonFPGA

This paper proposes two max-pooling engines, named the RTB-MAXP engine and the CMB-MAXP engine, with a scalable window size parameter for FPGA-based convolutional neural network (CNN) implementation. The max-pooling operation for the CNN can be decomposed into two stages, i.e., a horizontal axis max-pooling operation and a vertical axis max-pooling operation. These two one-dimensional max-pooling operations are performed by tracking the rank of the values within the window in the RTB-MAXP engine and cascading the maximum operations of the values in CMB-MAXP engine. Both the RBM-MAXP engine and the CMB-MAXP engine were implemented using VHSIC Hardware Description Language (VHDL) and verified by simulations. They have been employed for and tested in our CNN accelerator targeting at the CNN model YOLOv4-CSP-S-Leaky for object detection.

FPGA-based cards for data concentration and readout are often used in data acquisition (DAQ) systems for high-energy physics experiments. The DMA engines implemented in FPGA enable efficient data transfer to the processing system’s memory. This paper presents a versatile DMA engine. It may be used in systems with FPGA-equipped PCIe boards hosted in a server and MPSoC-based systems with programmable logic connected directly to the AXI system bus. The core part of the engine is implemented in HLS to simplify further development and modifications. The design is modular and may be easily integrated with the user’s DAQ logic, assuming it delivers the data via a standard AXI-Stream interface. The engine and accompanying software are designed with flexibility in mind. They offer a simple single-packet mode for debugging and a high-performance multi-packet mode fully utilizing the computational power of the processing system. The number of used DAQ cards and the amount of memory used for the DMA buffer may be modified in runtime without rebooting the system. That is particularly useful in the development and test setups. The paper also presents the development and testing methodology. The whole design is open-source and available in public repositories.

This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.

The concentration of data from multiple links to a single output is an essential task performed by High-Energy Physics (HEP) Data Acquisition Systems (DAQs). At high and varying data rates combined with the large width of the concentrator’s output interface, this task is non-trivial. This paper presents a concentrator based on the Beneš network, which provides efficient concentration without using a high-frequency clock internally. It warrants that empty data are eliminated and does not disturb the data time-ordering if the data rates significantly differ between inputs. Additionally, it is well suited to FPGA implementation. It is based on simple data-routing primitives and may be fully pipelined.

A portable laser photoacoustic sensor based on a Field-Programmable Gate Array (FPGA) is reported for methane detection. A tunable DFB diode laser in the 1654 nm wavelength range is used as an excitation source. The photoacoustic signal processing was implemented by a FPGA device. A small resonant photoacoustic cell is designed. The minimum detection limit (1σ) of 10 ppm for methane (CH₄) is demonstrated.

The synchronization of laser and X-ray sources is essential for time-resolved measurements in the study of ultrafast processes, including photo-induced piezo-effect, shock wave generation, and phase transition. On the one hand, the optical diagnostics (by synchronization of two laser sources) provides information about change in vibration frequencies, shock waves dynamics, linear and nonlinear refractive index behavior. On the other hand, the optical pump – X-ray probe diagnostics give opportunity to directly reveal the lattice dynamics. To integrate two approaches into a unified whole one need to create a robust method for synchronization of two systems with different repetition rate up to MHz range. In this paper, we propose a universal approach utilizing a field-programmable gate array (FPGA) to achieve precise synchronization between different MHz sources such as various lasers and synchrotron X-ray sources. This synchronization method offers numerous advantages, such as high flexibility, fast response, and low jitter. Experimental results demonstrate successful synchronization of two different MHz systems with a temporal resolution of 250 ps for these systems. This enables ultrafast measurements with sub-nanosecond resolution, facilitating the uncovering of complex dynamics in ultrafast processes.

The ZX Spectrum was a popular 8-bit home computer by Sinclair Research in the 80s. Even though some of these computers may still work, the audio tapes, the TV with an analog tuner and the micro-switch joystick, used with the original ZX Spectrum, nowadays are outdated and hard to find in good working order or replicate. Since many other old closed systems are also very difficult to update to support modern peripherals, there is a necessity to provide a methodology to adapt such systems to support new peripherals while being compatible with existing software. The work proposed in this paper is focused on recreating a ZX Spectrum+/48k computer and interface it with modern peripherals on an FPGA. This is accomplished by adding a co-processor to assist with the control of the new peripherals which would either require to complex architectural changes to the original system and in the end it would perform poorly due to the low performance of the Z80 CPU. This work distances from previous ones on emulating a ZX Spectrum since it focuses on the use of different upgraded peripherals and the use of a NIOS II soft-processor as a co-processor to manage the SD Card accesses. A demonstration of the proposed modernized architecture was made by successfully running a diagnostics ROM and playing original ZX Spectrum games from an SD card for game with a PS/2 keyboard and a pair of joysticks.

In the radar system, detection represents a basic and important stage in the receiver side. The detection process is based on the thresholding criteria; two philosophies of this criteria, constant and adaptive threshold. The constant threshold is simple in design, but it has a mis-detection and does not control the false alarm rate. As for the adaptive threshold, it is powerful in target detection, and better control of the false alarm rate, where it is called Constant False Alarm Rate (CFAR). Lots of research in the CFAR design, but the gap in the previous works is that there is no CFAR algorithm can be working with all or most environmental fields and all or most target situations.In this paper, The CFAR, which can work with the most environment and most of the target situations, has been presented. The producing the design and implementation of the new practical CFAR processor is presented. Where, the new CFAR is a combination of the properties of three different CFAR algorithm (CA, OSGO, and OSSO), and from two different families; averaging and statistical. Where it has overperformed of it's is 97.25% for simulation and 96.25% for the implementable version for different target situations. The simulation analysis is made by using Matlab 2015, while the implementation is done by using Xilinx Spartan 700 3a.

The Digital electronics collaborative enhanced learning (DECEL) project has recently developed an international collaborative education course. Its main objective is to enhance the digital electronics skills of international students by working on a complex, multidisciplinary applied problem using a mixed digital architecture. We have developed a logic level synthesis and dedicated software layers on the Red Pitaya FPGA platform. The diversity of digital concepts to be implemented, from hardware description language (HDL) to high-level languages such as Python or Matlab, forced the students to work together and rapidly improve their skills. Their motivation was fueled by the curiosity of controlling an ultrasound probe to obtain ultrasound signatures. This particular physics, little known to the students, was an additional source of curiosity. The goal of forming an image in a liquid medium was an additional motivating factor for them. The students reported that they learned a lot from the experiment. Thus, the technical parts and pedagogical results are documented in this work for reproducibility.

Graph Neural Networks (GNNs) are powerful models capable of managing intricate connections in non-Euclidean data, such as social networks, physical systems, chemical structures, and communication networks. Despite their effectiveness, the large-scale and complex nature of graph data demands substantial computational resources and high performance during both training and inference stages, presenting significant challenges, particularly in the context of embedded systems. Recent studies on GNNs have investigated both software and hardware solutions to enhance computational efficiency. Earlier studies on Deep Neural Networks (DNNs) have indicated that methods like reconfigurable hardware and quantization are beneficial in addressing these issues. Unlike DNN research, studies on efficient computational methods for GNNs are less developed and require more exploration. This survey reviews the latest developments in quantization and FPGA-based acceleration for GNNs, showcasing the capabilities of reconfigurable systems (often FPGAs) to offer customized solutions in environments marked by significant sparsity and the necessity for dynamic load management. It also emphasizes the role of quantization in reducing both computational and memory demands through the use of fixed-point arithmetic and streamlined vector formats. This paper concentrates on low-power, resource-limited devices over general hardware accelerators and reviews research applicable to embedded systems. Additionally, it provides a detailed discussion of potential research gaps, foundational knowledge, obstacles, and prospective future directions.

This paper details a design optimization on a hardware accelerator for an on-board real-time SAR imaging system using the Backprojection algorithm, focusing on algorithm-specific approximations intended to reduce the overhead introduced by intensive functions such as the square root, sine, and cosine functions. The main novelty of this work is that new approximations were investigated so that the final image retains high quality regardless of the error in the approximation function. This paper revisits existing approximation methods, such as linear interpolation, polynomial approximation using the Vandermonde matrix, and Chebyshev polynomials, and compares their performance on the algorithm. Results demonstrate that it is possible to maintain the image quality with an SSIM above 0.99 with less 93% LUTs for the square root and less 88% LUTs for the sine and cosine functions using polynomial approximation with the Vandermonde matrix when compared to the HLS baseline functions.

In recent years, Edge Intelligence (EI) has emerged, combining edge computing with AI, specifically deep learning, to run AI algorithms directly on edge devices. In practical applications, EI faces challenges related to computational power, power consumption, size, and cost, with the primary challenge being the trade-off between computational power and power consumption. This has rendered traditional computing platforms unsustainable, making heterogeneous parallel computing platforms a crucial pathway for implementing EI. In our research, we leveraged the Xilinx Zynq 7000 heterogeneous computing platform, employed High-Level Synthesis (HLS) for design, and implemented two different accelerators for LeNet-5 using loop unrolling and pipelining optimization techniques. The experimental results show that when running at a clock speed of 100 MHz, the PIPELINE accelerator, compared to the UNROLL accelerator, experiences an 8.09% increase in power consumption but speeds up by 14.972 times, making the PIPELINE accelerator superior in performance. Compared to the CPU, the PIPELINE accelerator reduces power consumption by 91.37% and speeds up by 70.387 times, while compared to the GPU, it reduces power consumption by 93.35%.This study provides two different optimization schemes for edge intelligence applications through design and experimentation, and demonstrates the impact of different quantization methods on FPGA resource consumption. These experimental results can provide a reference for practical applications, thereby providing a reference hardware acceleration scheme for edge intelligence applications.

Convolution forms one of the most essential operations for the FPGA-based hardware accelerator. However, the existing designs often neglect the inherent architecture of FPGA, which puts forward an austere challenge on hardware resource requirements. Even though some previous works have proposed approximate multipliers or convolution acceleration algorithms to deal with this issue, the inevitable accuracy loss and resource occupation easily lead to performance degradation. Toward this, we first propose two kinds of resource-efficient optimized accurate multipliers based on LUTs or carry chains. Then targeting FPGA-based platforms, a generic multiply-accumulate structure is constructed by directly accumulating the partial products produced by our proposed optimized radix-4 Booth multipliers without intermediate multiplication and addition results. Experimental results demonstrate that our proposed multiplier achieves a maximum 51% look-up-table (LUT) reduction compared to the Vivado area optimized multiplier IP. Furthermore, the convolutional process unit using the proposed structure achieves a 36% LUT reduction compared to existing methods. As case studies, the proposed method is applied to DCT transformer and LeNet to achieves hardware resource saving without loss of accuracy.

Chaotic switching is a newly evolve randomization method which can suppress conducted electromagnetic interference generated within the DC-DC converter. It can suppress the spectral peaks present in the frequency band effectively by spread spectrum technique and can spread it over the wide range of frequency band implying EMI suppression. In this paper, a chaotic PWM technique based on RCFMFD scheme is generated through Field programmable gate array (FPGA) for suppressing the conducted electromagnetic interference (EMI) generated within the Luo converter. A hardware prototype of Luo converter was developed in order to analyze EMI reduction through FFT analysis by comparing both traditional periodic PWM switching and chaotic PWM switching. The results obtained from the hardware setup shows significant reduction of EMI with Chaotic switching as compared to traditional PWM switching for both boost and buck operation of Luo converter.

This paper presents the design of a new neuro-generator of pseudorandom number type PRNG Pseudorandom Number Generator, which produces complex sequences with an adequate bit distri-bution. The circuit is connected to a neuronal module with six impulse neurons with different be-haviors: spike frequency adaptation, phasic spiking, mixed mode, phasic bursting, tonic bursting and tonic spiking. This module aims to generate a non-periodic signal that becomes the clock sig-nal for one of the LFSRs Linear Feedback Shift Register that the neuro-generator has. To verify its correct operation, the neuro-generator was subjected to a series of tests where the frequencies of the impulse neurons were modified. This modification allows generating a greater number of pulses at the output of the neuronal module, to obtain sequences with different characteristics that pass different NIST statistical tests National Institute of Standards and Technology of U.S. The results show that the new neuro-generator maintains pseudo-randomness in the sequences obtained with different frequencies and it can be implemented on reconfigurable FPGA Field Programmable Gate Array Virtex 7 xc7vx85t-2ffg1761 device. Therefore, it can be used for applications such as biologi-cal systems.

Spiking neural networks (SNNs) promise to perform tasks currently done by classical artificial neural networks (ANNs) faster, in smaller footprints and using less energy. Neuromorphic processors are set out to revolutionize computing at a large scale, but the move to edge-computing applications calls for finely-tuned custom implementations to keep pushing towards more efficient systems. To that end, we have examined the architectural design space for executing spiking neuron models on FPGA platforms, focusing on achieving ultra-low area and power consumption. This work presents an efficient clock-driven spiking neuron architecture used for the implementation of both fully-connected cores and 2D convolutional cores, which rely on deep pipelines for synaptic processing and distributed memory for weight and neuron states. With them, we have developed an accelerator for an SNN version of the LeNet-5 network trained on the MNIST dataset. At around 5.5 slices/neuron and only 348 mW, it is able to use 33% less area and 4 times as less power per neuron as current state-of-the-art implementations while keeping low simulation step times.

The advantage of FPGAs lies in the ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small "soft-core" processor implementing I/O in software. With the goal to design and evaluate a new tiny soft-core processor optimized for FPGA resources in I/O , a novel processor named Baby8 is developed. It is an 8-bit CISC soft-core processor optimized for reduced FPGA resources including program size for 8-bit applications. The number of instructions is not large but any instruction can access arbitrary memory locations. The performance and resource utilization of the newly designed processor are evaluated and compared with a variety of other soft-core processors. The results demonstrate its competitive performance, achieving an average maximum clock frequency of approximately 57 MHz and a power consumption of around 2mW. Furthermore, it conserves nearly half of the FPGA resources in implementation.

In recent years web applications and on-line business transactions have grown many folds. Consequently, also cyberattacks have increased and represent a serious threat to the pervasive digital services upon which our society relies. To mitigate cyberattacks, many countermeasures are deployed on computing nodes (e.g., anti-malware software) as well as on network devices to detect and possibly block malicious packets in transit; these monitoring devices broadly go under the name of firewalls. Firewalls are designed according to two main architectural approaches: software running on a standard or embedded computer, or purposedly designed hardware, e.g., ASICs. Software-based solutions have the advantage of high flexibility and can be ported on easily upgradable hardware. However, hardware implementation represents the only viable solution for high data rates. On the market, very fast devices of the latter kind are available, but their cost is typically very high, especially considering that their ultra-optimized design makes updating them very difficult, with the consequence of a rather short lifespan. As a more balanced alternative, we wanted to investigate the use of an FPGA architecture, , which is significantly easier to update than custom-built chips, and features low-latency and high-throughput characteristics concurrently, making it preferrable to other programmable systems based on GPUs or microcontrollers. In this paper a packet sniffer that has been designed on FPGA with a 1 Gbit/s data transfer rate is presented. The system is implemented on the FPGA development board KC705 by Xilinx, can analyze Ethernet frames, checking the frame fields against a set of rules defined by the user and calculates statistics of the received Ethernet frames over time. The designed packet sniffer has been successfully tested both with Ethernet frames ad hoc generated using a packets generator, and with real web traffic by connecting the packet sniffer to the internet.

Due to the advantages of low latency, low power consumption and high flexibility of FPGA-based acceleration technology, it has been more and more widely studied and applied in the field of computer vision in recent years. An FPGA-based feature extraction and tracking accelerator for real-time visual odometry (VO) and visual simultaneous localization and mapping (V-SLAM) is proposed, which can realize the complete acceleration processing capability of the image front-end and directly output the feature point ID and coordinates to the backend. The accelerator consists of image preprocessing, pyramid processing, optical flow processing, and feature extraction and tracking modules. For the first time, it implements a hardware solution that combines features from accelerated segment test (FAST) corners with Gunnar Farneback (GF) dense optical flow, to achieve better feature tracking performance and provide more flexible technical route selection. In order to solve the scale invariance and rotation invariance lacking problem of FAST features, an efficient pyramid module with a five-layer thumbnail structure is designed and implemented. The accelerator is implemented on a modern Xilinx Zynq FPGA. The evaluation result shows that the accelerator can achieve stable tracking of features of violently shaking images, and is consistent with the results of MATLAB code running on PC. When operating at 100MHz, the accelerator can process 108 frames per second for 720P images and 48 frames per second for 1080P images. Compared to PC CPUs that consume seconds of time, the processing latency is greatly reduced to the order of milliseconds, making GF dense optical flow an efficient and practical technical solution on the edge side.

This paper presents a comprehensive study and the analysis of a topology of a no isolated DC-DC intituled Double Quadratic Boost converter with high static gain. This converter has the main advantage of high static gain and low voltage stress on its switches. The article will first present the theoretical analysis of the converter operating in an open loop. The objective of the work is the mathematical modeling and the control strategy of the converter, as well as the validation through closed-loop experimental results. Besides, we presented the practice test results to demonstrate the operation of the converter, such as the static gain experimental curve, the practice efficiency of the converter, and the control of the output voltage, as well as the capacitor voltage balance control. The authors designed a prototype for 1 kW, with a switching frequency of fs=50kHz, with FPGA-based command and modulation.

To build a stable power factor and high output accuracy, it should use balanced active and reactive power, also used ultrasonic PWM was used with the frequencies (20–500 kHz). I also used a three-phase dynamic load at the output system and was connected to the compound splicing (CS) system this is a novelty. An oscillator circuit with 4Ghz as a microcontroller is a novelty, and designing ADC is utilized to increase accuracy, as well as contribute to the reduction of loss brought on by the characteristics of voltage source inverters (VSI), such as dead time determined by the excess voltage or voltage drop in the inverter, circumstances abnormal to the load current, such as short circuit current in the production phase, and so forth. The innovation relates to the inverter's load sensing circuit, current smoothing during operation, reaction, spontaneous power factor enhancement of the inverter, and correction of reactive power of passive devices. This invention contributes to the advancement of D.C to A.C power converter by the achievement of extremely low losses, excellent precision, and lightweight construction. Additionally, the accuracy ranges from 99%, and the total harmonic distortion (THD) of the voltage and current is (0.1%-0.8%). We Power MOSFET are used, along with FPGA to improve control over the creation of ultrasonic PWM signals, the programmable peripheral interface (PPI) 8255A for regulatory work. The marks serve as proof of this.

FPGA-based data acquisition and processing systems play an important role in modern high-speed, multichannel measurement systems, especially in High-Energy and Plasma Physics. Such FPGA-based systems require an extended control and diagnostics part corresponding to the complexity of the controlled system. Managing the complex structure of registers while keeping the tight coupling between hardware and software is a tedious and potentially error-prone process. Various existing solutions aimed at helping that task do not perfectly match all specific requirements of that application area. The paper presents a new solution based on the XML system description, facilitating the automated generation of the control system’s HDL code and software components and enabling easy integration with the control software. The emphasis is put on reusability, ease of maintenance in case of system modification, easy detection of mistakes, and the possibility of use in modern FPGAs. The presented system has been successfully used in data acquisition and preprocessing projects in High-Energy Physics experiments. It enables easy creation and modification of the control system definition and convenient access to the control and diagnostic blocks. The presented system is an open-source solution and may be adopted by the user for particular needs.

Interferometry is used in magnetic fusion devices to measure the line-1 averaged electron density. It is based on detecting changes in the refractive index of electromagnetic waves traveling through a plasma. The adequate frequency of these electromagnetic waves depends on several limitations. First the maximum expected peak electronic density must be lower than the cutoff density for that frequency. This means that the waves can still propagate through the plasma when the maximum density is reached. In this sense, IR interferometers operating in the infrared región are themost suitable. With such low wavelengths, mechanical vibrations become an important issue and a complementary interferometer to cancel these vibrations must be used. These arrangements are called two color interferometers. In this paper some measurements that were obtained from the TJ-II double color IR FPGA-based processing system that were never published before are shown and analyzed. The line-averaged electron density is computed in real time (100 μs).

The paper proposes a new implementation of the PID algorithm in digital hardware. The proposed circuit implements an advanced PID formula, containing a non ideal derivative component, and weighting coefficients, which enable reducing influence of setpoint changes in the proportional and derivative components. The implementation operates on standard single precision (32 bit) floating-point numbers. The proposed circuit structure is optimized for cost. It uses just one arithmetic block, performing the multiply-and-add operation. The calculations are carried out in a sequential manner. The circuit was implemented in a Cyclone V FPGA device from Intel, using the Quartus Prime software. Proper operation of the circuit was verified by simulation. The proposed solution is comparable in terms of speed with other hardware implementations of the PID algorithm operating on standard single precision floating-point numbers, while being significantly cheaper. However, it outperforms by several orders of magnitude the speed of any software-based implementation, including solutions using PLCs, and CPU/MCUs. The proposed circuit structure, together with the overall regulator device concept, suit well the SoC (System on Chip), or SoPC (System on Programmable Chip) idea, i. e. a device, that contains a CPU core immersed in “FPGA fabric” - logic resources characteristic for FPGA devices.

This research investigates the implementation of complex exponential-based neurons in FPGA, which can pave the way for implementing bio-inspired spiking neural networks to compensate for the existing computational constraints in conventional artificial neural networks. The increasing use of extensive neural networks and the complexity of models in handling big data lead to higher power consumption and delays. Hence, finding solutions to reduce computational complexity is crucial for addressing power consumption challenges. The complex exponential form effectively encodes oscillating features like frequency, amplitude, and phase shift, streamlining the demanding calculations typical of conventional artificial neurons through levering simple phase addition of complex exponential functions. The article implements such a two-neuron and a multi-neuron neural model using Xilinx system generator and Vivado design suite, employing 8-bit, 16-bit, and 32-bit fixed-point data format representations. The study evaluates the accuracy of the proposed neuron model across different FPGA implementations while also providing a detailed analysis of operating frequency, power consumption, and resource usage for the hardware implementations. BRAM-based Vivado designs outperformed Simulink regarding speed, power, and resource efficiency. Specifically, the Vivado BRAM-based approach supported up to 128 neurons, showcasing optimal LUT and FF resource utilization. Such outcomes accommodate choosing the optimal design procedure for implementing spiking neural networks on FPGAs.

Edge computing has emerged as a significant computing trend alongside the rapid expansion of the Internet of Things (IoT). Computing operations at the network’s edge offer a solution to the high latency and service overload challenges often associated with cloud computing. Additionally, the Secure Hash Algorithm-3 (SHA-3) plays a crucial role in ensuring data integrity and is implemented for numerous applications in the IoT field. Therefore, integrating the SHA-3 accelerator into edge computing is essential. Moreover, recent studies about SHA-3 have primarily focused on achieving high performance and optimizing resource utilization for SHA-3. However, these studies have overlooked the crucial aspect of data transfer between the external memory and the hash function block, as transfer time plays a significant role. This paper proposes an efficient SHA-3 architecture designed for System-on-Chip (SoC) Field Programmable Gate Array (FPGA) to address the aforementioned challenges and be suitable for real edge computing. The architecture contains three key techniques. First, the harmony of padding and Direct Memory Access (DMA) for managing the data transfer process and enhancing performance efficiency based on Serial Input to Parallel Output (SIPO) and a barrel shifter. Secondly, implementing internal pipelining within the Round Function (RF) to reduce critical path delays and optimize resource utilization. Finally, designing four modes (SHA3-224, SHA3-256, SHA3-384, and SHA3-512) to cater to various applications. Our architecture is implemented and tested on the DE10-Standard Development Kit (Cyclone V SX SoC-5CSXFC6D6F31C6N), which is integrated into the FPGA and is controlled by a Dual-Core ARM Cortex-A9 processor. The result is up to 38.34 Gbps in throughput and 5.61 Mbps/ALM in efficiency for the RF computation, 28.02 Gbps in throughput, and 3.63 Mbps/ALM for the full proposed architecture.

Orbitrap mass spectrometers have been widely used in environmental component analysis . This paper presents an enhanced data acquisition system for in-situ detection of Orbitrap mass spectrometry, which enables in-suit real-time signal processing and analysis for atmospheric molecules with small mass numbers.During previous space atmospheric explorations, quadrupole mass spectrometry (QMS) was usually utilized for analyzing isotopic compositions and complicated compounds in the mixture. However, the inevitable ion scattering and drift during mass transfer, as well as the QMS attenuator loss, result in a relatively lower signal-to-noise ratio of the produced mass spectrum. In recent years, a novel mass spectrometer, called an Orbitrap mass spectrometer, has been gradually accepted and used because of its non-destructive detection ability, high mass resolution, and accuracy. Nevertheless, Fourier transform ion cyclotron resonance mass spectrometry (FT-ICR MS) is preferred over the Orbitrap mass spectrometry for ground applications, especially for detecting low-mass components (e.g. below 50 atomic mass units) due to the former’s superior resolution. As the mass number decreases, the detection system demands a higher sampling and processing rate. Additionally, in ground-based scenarios, mass spectrometry analysis software on computers is often employed to analyze the signals. Therefore, in order to achieve in-situ detection of the space atmospheric environment using the Orbitrap mass spectrometer, this paper proposes a real-time signal acquisition and processing system for mass spectrometry analysis. The system comprises of signal conditioning circuits, analog-to-digital conversion circuits, programmable logic circuits, and related software. These components perform spectrum analysis and process the signal in real-time on hardware components, allowing for high-speed acquisition and analysis of the signals produced by the Orbitrap mass spectrometer.

This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximizes the sharing of common hardware circuit and achieves the area-delay-efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 1638416384 points target Synthetic Aperture Radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T FPGA platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.

The exponential growth and widespread adoption of Internet of Things (IoT) devices have introduced many vulnerabilities. Attackers frequently exploit these flaws, necessitating advanced technological approaches to protect against emerging cyber threats. This study introduces a novel approach utilizing hardware honeypots as an additional defensive layer against hardware vulnerabilities, particularly hardware trojans (HTs). HTs pose significant risks to the security of modern integrated circuits (ICs), potentially causing operational failures, denial of service, or data leakage through intentional modifications. The proposed system was implemented on a Raspberry Pi and tested on an emulated HT circuit using a Field-Programmable Gate Array (FPGA). This approach leverages hardware honeypots to detect and mitigate HTs in IoT devices. The results demonstrate that the system effectively detects and mitigates HTs without imposing additional complexity on the IoT devices. The trojan-agnostic solution offers full customization to meet specific security needs, providing a flexible and robust layer of security. The findings provide valuable insights into enhancing the security of IoT devices against hardware-based cyber threats, thereby contributing to the overall resilience of IoT networks. This innovative approach offers a promising solution to address the growing security challenges in IoT environments.

The implementation of neural networks (NN) on edge devices enables local processing of wireless data but faces challenges such as high computational complexity and memory requirements when deep neural networks (DNN) are used. Shallow neural networks customized for specific problems are more efficient, requiring fewer resources, and resulting in a lower latency solution. An additional benefit of the smaller network size is that it is suitable for real-time processing on edge devices. The main concern with shallow neural networks is their accuracy performance compared to DNNs. In this paper, we demonstrate that a customized adaptive activation function (AAF) can meet the accuracy of a DNN. We designed an efficient FPGA implementation for a customized segmented spline curve neural network (SSCNN) structure to replace the traditional fixed activation function with an AAF. We compared our SSCNN with different neural network structures such as real-valued time delay neural network (RVTDNN), augmented real-valued time delay neural network (ARVTDNN), and deep neural networks with different parameters. Our proposed SSCNN implementation uses 40% fewer hardware resources and no Block RAMS compared to the DNN with similar accuracy. We experimentally validate this computationally efficient and memory-saving FPGA implementation of SSCNN for digital predistortion of RF power amplifiers using the AMD/Xilinx RFSoC ZCU111. The implemented solution uses less than 3% of the available resources. The solution also enables an increase of the clock frequency to 221.12 MHz, allowing the transmission of wide bandwidth signals.

Nowadays, there are implemented devices whose purpose is to perform massive computations by saving resources at the time they reduce the latency of arithmetic operations. These devices are usually GPUs, FPGAs and other specialised devices such as "Coral". Neural networks, digital filters and numerical simulators take advantage of the massively parallel operations of such devices. One way to reduce the amount of resources used is to limit the size of the registers that store data. This has led to the proliferation of numeric formats with a length of less than 32 bits, known as short floating point or SFP. We have developed several SFP’s for use in our neural network accelerator design, allowing for different levels of accuracy. We use a 16-bit format for data transfer and different formats can be used simultaneously for internal operations. The internal operations can be performed in 16-bit, 20-bit and 24-bit. The use of registers larger than 16-bit allows the preservation of fractional information while increasing precision. By leveraging some of the FPGA’s arithmetic resources, our design outperforms designs implemented from scratch and is competitive with specialized arithmetic circuits already implemented in the FPGA.

The Physical Random Access Channel (PRACH) plays an important role in LTE and LTE-A systems. It is through the PRACH channel that the user equipment (UE), based on eNodeB's timing estimates, aligns its uplink transmissions to the eNodeB's uplink and gain access to the network. One of the initial operations executed by the PRACH receiver at eNodeB side is the translation of the PRACH signal back to base band, $i.e.$, center the PRACH signal around DC. This operation is a necessary step for preamble detection and can be carried out through a time-domain frequency shift operation. Therefore, in this paper we present the hardware architecture and implementation details of a configurable and optimized FPGA-based time-domain frequency shifter. It is a hardware-efficient and accurate architecture for converting the relevant received PRACH signal into base band before further signal processing. The architecture is manly based on a customized Numerically Controlled Oscillator (NCO), which is used for generating complex exponentials employing only adders, a Look-Up Table (LUT) and plain logic resources. The main advantage of the proposed hardware architecture is that it completely eliminates the need for storing a large number of long complex exponential sequences by employing a single LUT and exploiting quarter wave symmetry of the basis waveform. Our simulation results show that the proposed customized NCO architecture provides high Spurious Free Dynamic Range (SFDR) signals using a minimal amount of FPGA resources. Moreover, the proposed architecture exhibits spur-suppression ranging from 62.13 to 153.58 dB without using Taylor Series correction.

This study presents the design and implementation of a PLC microprocessor adhering to the IEC-61131-3 standard, executed on a Cyclone-V FPGA using a DE10-NANO development board. Our microprocessor optimizes the central processing unit by streamlining the data path, achieving a remarkable simulated response time of approximately 60 ns, equivalent to three clock cycles at a 50MHz frequency for Boolean operations. To substantiate our approach, we conducted practical experiments utilizing a FESTO conveyor station, employing relays as actuators, and incorporating optical and inductive sensors. The results underscore the feasibility of our proposed approach and serve as practical validation of its efficacy. This work introduces a promising avenue for the development of cost-effective PLCs employing SoC FPGA variants. Additionally, a thorough comparison of execution times with other early reported architectures. Our microprocessor outperforms even well-established PLCs like the S7-312, with substantial reductions in execution times of 94.54% for floating-point operations, 71.42% to 93.33% for word operations, and up to 78.57% for bit operations.

Video behavior recognition often needs to focus on object motion processes. In this work, a self-organizing computational system oriented to behavioral clustering recognition is proposed, which achieves the extraction of motion change patterns by binary encoding and completes motion pattern summarization using a similarity comparison algorithm. And in the face of unknown behavioral video data, a self-organizing structure with layer-by-layer accuracy progression is used to achieve motion law summarization by using a multi-layer agent design approach. Finally, the real-time feasibility is verified in the prototype system using real scenes to provide a new feasible solution for unsupervised behavior recognition and space-time scenes.

This paper first discusses a fractional-order Liu system of order as low as 2.7 and shows its chaotic characteristics by carrying out numerical simulations such as Lyapunov exponents, bifurcation diagrams and phase portraits. Then, by using the topological horseshoe theory and computer-assisted proof, the existence of chaos in the system is verified theoretically. Finally, the fractional-order system is implemented on a Field Programmable Gate Array (FPGA) and the results obtained show that the fractional-order Liu system is indeed chaotic.

Digital image compression is applied to reduce camera bandwidth and storage requirements, but real-time lossless compression on a high-speed high-resolution camera is a challenging task. The article presents hardware implementation of a Bayer colour filter array lossless image compression algorithm on an FPGA-based camera. The compression algorithm reduces colour and spatial redundancy and employs Golomb-Rice entropy coding. A rule limiting the maximum code length is introduced for the edge cases. The proposed algorithm is based on integer operators for efficient hardware implementation. The algorithm is first verified as a C++ model and later implemented on Xillinx Zynq UltraScale+ device using VHDL. An effective tree-like pipeline structure is proposed to concatenate codes of compressed pixel data to generate a bitstream representing data of 16 parallel pixels. The proposed parallel compression achieves up to 56% reduction in image size for high resolution images. Pipelined implementation without any state machine ensures operating frequencies up to 320 MHz. Parallelised operation on 16 pixels effectively increases data throughput to 40 Gbit/s while keeping total memory requirements low due to real-time processing.

In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and it is important to evaluate their performance in specific use cases. This paper evaluates the energy consumption and resource utilization of a new RISC-V processor, RisCO2, and four existing processors - Zero-riscy, Micro-riscy, Ri5cy, and CV32E40P - in a signal demodulation application for NDIR CO2 sensors. The processors were implemented in the PULPino SoC and synthesized using Vivado IDE. The processor named RisCO2 is based on the RV32E_Zfinx instruction set and was designed from scratch by the authors specifically for low-power signal processing applications such as signal demodulation in CO2 NDIR sensors. The other processors are Ri5cy, Micro-riscy, and Zero-riscy, developed by the PULP Platform team, and CV32E40P (derived from Ri5cy) from the OpenHW Group, all of them widely used in the RISC-V community. Our experiments showed that RisCO2 had the lowest energy consumption among the five processors, with a 53.5% reduction in energy consumption compared to CV32E40P and a 94.8% reduction compared to Micro-riscy. Additionally, RisCO2 had the lowest FPGA resource utilization compared to the best-performing processors, CV32E40P and Ri5cy, with a 46.1% and a 59% reduction in LUTs, respectively. Our findings suggest that RisCO2 is a highly energy-efficient RISC-V processor for NDIR CO2 sensors that require signal demodulation. The results also highlight the importance of evaluating processors in specific use cases to identify the most energy-efficient option. This paper provides valuable insights for designers of energy-efficient embedded systems using RISC-V processors.

Many dedicated designs for real-time operations provide functionality on fixed-sized operators, but where speed, scalability, and flexibility are required, extensive research is demanded. Dedicated designs can provide real-time processing for many applications. This paper presents an FPGA-based design of a general image processor. The proposed design is based on a fixed-point representation of binary numbers. The proposed design provides a mechanism to manage matrices on-chip along with matrix arithmetic. The matrices are represented with simple identifiers and microinstruction that assist in the computation of many operations which are useful for solving complex problems. The design was successfully implemented and tested using VHDL language. The proposed design is an efficient architecture as a standalone processor with all embedding computational resources necessary for an embedded image processing application.

An exploding demand for processing capabilities related to the emergence of the IoT, AI and big data, has led to the quest for increasingly efficient ways to expeditiously process the rapidly increasing amount of data. These ways include different approaches like improved devices capable of going further in the more Moore path, but also new devices and architectures capable of going beyond Moore and getting more than Moore. Among the solutions being proposed, Stochastic Computing has positioned itself as a very reasonable alternative for low-power, low-area, low-speed, and adjustable precision calculations; four key-points beneficial to edge computing. On the other hand, chaotic circuits and systems appear to be an attractive solution for (low-power, green) secure data transmission in the frame of edge computing and IoT in general. Classical implementations of this class of circuits require intensive and precise calculations. This paper discusses the use of the SC framework for the implementation of nonlinear systems, showing that it can provide results comparable to those of classical integration, with much simpler hardware, paving the way for relevant applications.

Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry. As the target architecture evolves, it also needs to be updated remotely on the target platform. This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration. This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates. The proposed framework implements secure boot protocol on Xilinx based FPGAs. The project demonstrates the configuration of the bitstream, boot process integration with TPM and secure over-the-air updates for the hardware reconfiguration.

Few switching transitions in high power and medium voltage application of Power converters are desirable. The selective harmonics elimination (SHE) pulse width modulation offers a better quality waveform with lower switching transitions and hence lower switching losses. The SHE is a pre-programmed modulation technique where certain amounts of lower order harmonics are removed and fundamental voltage is controlled. After Fourier analysis of output waveform, a set of nonlinear transcendental equations is obtained which exhibits, multiple, unique or no solution in different range of modulation index (MI). In this paper, an iterative method based on the Jacobian estimate is proposed to solve a highly non-linear set of SHE equations. The proposed technique is easy in implementation and can solve a large number of such equations as computation of the Jacobian matrix in the subsequent iteration is estimated from the previous values. Moreover, the proposed method also removes the singularity problem, especially for large SHE equations. High accuracy in the initial guess is also not essential for this method and can converge to the solution with any random initial guess. The computational and simulation results are given to validate the concept. The hardware result is provided to confirm the computational and simulation results.

Optical wireless video transmission technology combines the advantages of high data rates, enhanced security, large bandwidth capacity, and strong anti-interference capabilities inherent in optical communication, establishing it as a pivotal technology in contemporary data transmission networks. However, video data comprises a large volume of image information, resulting in substantial data flow with significant redundant bits. To address this, we propose an adaptive block sampling compressive sensing algorithm that overcomes the limitations of sampling inflexibility in traditional compressive sensing, which often leads to either redundant or insufficient local sampling. This method significantly reduces the presence of redundant bits in video images. First, the sampling mechanism of the block-based compressive sensing algorithm was optimized. Subsequently, a wireless optical video transmission experimental system was developed using a Field-Programmable Gate Array chip. Finally, experiments were conducted to evaluate the transmission of video optical signals. The results demonstrate that the proposed algorithm improves the Peak Signal-to-Noise Ratio by over 3 dB compared to other algorithms, with an enhancement exceeding 1.5 dB even in field tests, thereby significantly optimizing video transmission quality. This research contributes essential technical insights for the enhancement of wireless optical video transmission performance.

With the current technological transformation in the automotive industry, autonomous vehicles are getting closer to the Society of Automative Engineers (SAE) automation level 5. This level corresponds to the full vehicle automation, where the driving system autonomously monitors and navigates the environment. With SAE-level 5, the concept of a Shared Autonomous Vehicle (SAV) will soon become a reality and mainstream. The main purpose of an SAV is to allow unrelated passengers to share an autonomous vehicle without a driver/moderator inside the shared space. However, to ensure their safety and well-being until they reach their final destination, it is required an active monitoring of all passengers. In this context, this article presents a microphone-based sensor system that is able to localize sound events inside an SAV. The solution is composed of a Micro-Electro-Mechanical System (MEMS) microphone array with a circular geometry connected to an embedded processing platform that resorts to Field-Programmable Gate Array (FPGA) technology to successfully process in hardware the sound localization algorithms.

Cloud Computing is a promising and emerging technology that is rapidly being adopted by many IT companies due to a number of benefits that it provides, such as large storage space, low investment cost, virtualization, resource sharing, etc. Users are able to store a vast amount of data and information in the cloud and access it from anywhere, anytime on a pay-per-use basis. Since many users are able to share the data and the resources stored in the cloud, there arises a need to provide access to the data to only those users who are authorized to access it. This can be done through access control schemes which allow the authenticated and authorized users to access the data and deny access to unauthorized users. In this paper, a comprehensive review of all the existing access control schemes has been discussed along with analysis. Keywords: role-based access control, attribute-based access control, attribute-based encryption

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes DSP primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020, yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

The increasing adoption of student-centred learning environs by the institutions of higher education in business, has led to new mechanisms and methodologies such as the Simulation-Based Learning (SBL), Problem-Based Learning (PBL) and Challenge-Based Learning (CBL). Literature has shown evidence of raising interest in these methodologies towards a more experiential paradigm with regard to upcoming events from the surrounding real-world context. This paper presents a Systematic Bibliographic Literature Review (SBLR) with respect to the integration and application of these innovative and collaborative methodologies in higher education. It aimed to identify its relevant advantages, challenges, and consequences for the future of business education. Bibliographic databases were searched for documents published up to May 2024 to categorize key topics discussed in the literature on SBL, PBL and CBL. The review process identified 89 empirical and non-empirical papers on SBL, PBL and CBL, business related paperwork, which resulted from the PRISMA (Preferred Reporting Items for Systematic Reviews and Meta-Analyses) method. PRISMA is a framework with evidence-based data designed to help authors perform a systematic literature review. Data analysis revealed diverse subthemes for those methodologies uses in business higher education institutions. The research questions “What are the advantages, challenges and implications of SBL, PBL and CBL altogether, in the training of business students?” guided the study. The central output of the research is the discovery of the varying uses of SBL, PBL and CBL overall, to cope with diverse demands arising within environmental context. Future research directions are suggested.

With the development of satellite load technology and very-large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. Limited by severe size, weight, and power consumption constraints, a key challenge of on-board SAR imaging system design is to achieve high real-time processing performance. In addition, with the rise of multi-mode SAR applications, the reconfiguration of the on-board processing system is beginning to receive widespread attention. This paper presents a multi-mode SAR imaging chip with SoC architecture based on the reconfigurable double-operation engines and multilayer switching network. We decompose the commonly used extend chirp scaling (CS) SAR imaging algorithm into 8 types of double-operation engines according to the computing orders, and design a three-level switching network to connect these engines for data transition. The CPU is responsible for engine scheduling based on data flow driven with instructions to implement each part of the CS algorithm. Thus, multi-mode floating-point SAR imaging processing can be integrated into a single Application-Specific Integrated Circuit (ASIC) chip instead of relying on distributed technologies. As a proof of concept, a prototype measurement system with chip-included board is implemented, and the performance of the proposed design is demonstrated on Chinese Gaofen-3 stripmap continuous imaging. A chip requires 9.2 s, 50.6 s and 7.4 s for a stripmap with 16,384×16,384 granularity, multi-channel stripmap with 65.536×8192 granularity and multi-channel scan mode with 32,768×4096 granularity and 6.9 W for the system hardware to process the SAR raw data.

On using a 3D model to teach students a topic in astronomy, feedback was evaluated via a questionnaire. Analysis of students' responses to the questions revealed that user interface had a significant impact on their attitudes, which in turn could increase users' willingness to use immersive technology in e-learning. The results also showed that improving visual features through immersive technology and augmented reality tools were effective. The results confirm all hypotheses about positive relationships between facilitating conditions and usability of metaverse technology for students' attention and study motivation.

In recent years there has been an increasing interest in developing novel materials based on natural biopolymers as a renewable alternative of petroleum-based plastics. The availability of proteins derived from agricultural by-products, along with their favourable properties, has fostered a renewed interest in protein-based materials, promoting research in innovative technologies. In this study we propose the use of rapeseed protein-rich meal as main ingredient for the preparation of novel sustainable materials combining excellent environmental properties such as biodegradability and renewable origin. Application as sustainable products in the present high-tech society needs modification of basic native properties of these natural compounds. The original route proposed in this paper consists in the preparation via compression moulding of flexible biomaterials stabilized by crosslinkers/chain extenders. Investigation of the effects of different denaturing and disulfide bond reducing agents, crosslinkers, and preparation conditions on the material mechanical behaviour demonstrated that the novel materials have appreciable strength and stiffness. The results show the potential of utilizing full meal from vegetable by-products to prepare protein-based materials with granted ecofriendly characteristics and mechanical properties adequate to specific structural applications.

The firmware developed for the readout and trigger processing of the information emerging from BIS78-RPC Muon Spectrometer chambers in the ATLAS experiment at CERN, is presented here, together with data processing techniques, data acquisition software and tests of the readout chain system, on the road to make these chambers operational in the ATLAS experiment. This work is performed in the context of the BIS78-RPC project, which deals with the pilot deployment of a new generation of sMDT+RPC chambers in the experiment. Such chambers are planned to be fully deployed in the whole barrel inner layer of the Muon Spectrometer during the Phase-II upgrade of the ATLAS experiment. On-chamber front-ends include an amplifier, a discriminator ASIC and an LVDS transmitter. The signal is digitized by CERN HPTDC chips and then processed by an FPGA which is the heart of the readout and trigger processing, using various techniques. The work presented here is a continuation of the work presented in [1].

Nowadays, unmanned vehicles are widely used in various fields. However, the safety of unmanned vehicles is directly determined by the autopilot systems, and sensor faults are a very critical factor that affects the normal operation of the autopilot systems. To efficiently and comprehensively test unmanned systems for sensor faults, this paper proposes a chip-level testing platform for unmanned vehicle autopilot systems based on FPGA hardware-in-the-loop simulation. Unlike existing testing platforms, the introduction of FPGA technology allows us to achieve nanosecond real-time simulation frequency, thus realizing chip-level simulation of sensors and black-box automated testing. Firstly, we propose a set of general platform and modeling methods, and the paper presents a detailed application of the four most common necessary sensors in autopilot systems as examples. Secondly, we propose for the first time a chip-level fault testing method for unmanned systems, and build a test platform with a quadrotor vehicle, the PX4 software platform, and the Pixhawk4 hardware platform as examples. Finally, the experimental results verify that the testing platform proposed in this paper can adapt to various autopilot systems and has high simulation test reliability.

Many theoretical models of iron-based superconductors have been proposed but Tc calculations based on the models are usually missing. We have chosen two models of iron-based superconductors in the literature and then compute the Tc values accordingly: Recently two models have been announced which suggest that superconducting electron concentration involved in the pairing mechanism of iron-based superconductors may have been underestimated, and that the antiferromagnetism and the induced xy potential may even have a dramatic amplification effect on electron-phonon coupling. We use bulk FeSe, LiFeAs and NaFeAs data to calculate the Tc based on these models and test if the combined model can predict the superconducting transition temperature (Tc) of the nanostructured FeSe monolayer well. To substantiate the recently announced xy potential in the literature, we create a two-channel model to separately superimpose the dynamics of the electron in the upper and lower tetrahedral plane. The results of our two-channel model support the literature data. While scientists are still searching for a universal DFT functional that can describe the pairing mechanism of all iron-based superconductors, we base on the ARPES data to propose an empirical combination of DFT functional for revising the electron-phonon scattering matrix in the superconducting state, which ensures that all electrons involved in iron-based superconductivity are included in the computation. Our computational model takes into account this amplifying effect of antiferromagnetism and the correction of the electron-phonon scattering matrix together with the abnormal soft out-of-plane lattice vibration of the layered structure, which allows us to calculate theoretical Tc values of LiFeAs, NaFeAs and FeSe as a function of pressure that correspond reasonably well to the experimental values. More importantly, by taking into account the interfacial effect between an FeSe monolayer and its SrTiO3 substrate as an additional gain factor, our calculated Tc value is up to 91 K high, and provides evidence that the strong Tc enhancement recently observed in such monolayers with Tc reaching 100 K may be contributed from the electrons within the ARPES range.

One of the efficient data mining tools is density-based clustering, including the density grid-based clustering. However, a common drawback always existing in clusters made by the density grid-based method is the existence of weakly connected grids deriving mainly from noise. Appearing such an unwanted connection with a high frequency reduces the accuracy of the obtained cluster data space (CDS) and its application efficiency. Here, we present an essential improvement to overcome this problem. First, we describe a concept of the weak-connected grid cell (WCG) and present a fuzzy-type approximation to depict the density-based distribution of data points at grid nodes. Then, we propose a strategy of searching WCG for density grid-based clustering (SWCG-DGB) to set up a CDS, filter noise, and tune the created CDS. A buffer is deployed during this phase to collect border points and filter noise, which improves the computational time significantly, especially for noisy datasets. Results from numerical surveys reflected the compared efficiency of this method in clustering validity, including the accuracy of the number of clusters.

Mycobacterium tuberculosis (Mtb) is the etiological agent of tuberculosis (TB), a disease that alt-hough preventable and curable, remains a global epidemic due to the emergence of resistance and a latent form responsible for a long period of treatment. Drug discovery in TB is a challenging task due to the heterogeneity of the disease, the emergence of resistance and an uncomplete knowledge of the pathophysiology of the disease. The limited permeability of the cell wall and the presence of multiple efflux pumps remain a major barrier to achieve effective intracellular drug accumulation. While the complete genome sequence of Mtb has been determined and several potential protein targets have been validated, the lack of adequate models for in vitro and in vivo studies is a limit-ing factor in TB drug discovery programs. In current therapeutic regimens, less than 0.5% of bac-terial proteins are targeted being the biosynthesis of the cell wall and the energetic metabolism two of the most important processes exploited for TB chemotherapeutics. This review provides an overview on the current challenges in TB drug discovery and emerging Mtb druggable proteins, and how chemical probes for protein profiling enabled the identification of new targets and bi-omarkers, paving the way to disruptive therapeutic regimens and diagnostic tools.

Lake Rawapening, Semarang Regency, Indonesia, has incorporated a holistic plan in its management practices. However, despite successful target achievements, some limitations remain that a review of its management plan is needed. This paper identifies and analyzes existing lake management strategies as a standard specifically in Lake Rawapening by exploring various literature, both legal frameworks and scholarly articles indexed in Google Scholar and published in Water by MDPI about lake management in many countries. There are two major types of lake management, namely pillar-based and object-based. While the former is the foundation of a conceptual paradigm that does not comprehensively consider the roles of finance and technology in the lake management, the latter indicates the objects to manage so as to create standards or benchmarks for the implementation of various programs. Overall, Lake Rawapening management should include more programs on erosion-sedimentation control and monitoring of operational performance using information systems.

Nature-based solutions (NbS) are increasingly recognised for their potential to address both the climate and biodiversity crises. These outcomes are interdependent, and both rely on the capacity of NbS to support and enhance the health of an ecosystem: its biodiversity, the condition of its abiotic and biotic elements, and its capacity to function normally despite environmental change. However, while understanding of ecosystem health outcomes of nature-based interventions for climate change mitigation is growing, the outcomes of those implemented for adaptation remain poorly understood with evidence scattered across multiple disciplines. To address this, we conducted a systematic review of the outcomes of 109 nature-based interventions for climate change adaptation using 33 indicators of ecosystem health across eight broad categories (e.g. diversity, biomass, ecosystem functioning and population dynamics). We showed that 88% of interventions with positive outcomes for climate change adaptation also reported measurable benefits for ecosystem health. We also showed that interventions were associated with a 67% average increase in local species richness. All eight studies that reported benefits in terms of both climate change mitigation and adaptation also supported ecosystem health, leading to a triple win. However, there were also trade-offs, mainly for forest management and creation of novel ecosystems such as monoculture plantations of non-native species. Our review highlights two major limitations of research to date. First, only a limited selection of metrics are used to assess ecosystem health and these rarely include key aspects such as functional diversity and habitat connectivity. Second, taxonomic coverage is poor: 67% of outcomes assessed only plants and 57% did not distinguish between native and non-native species. Future research addressing these issues will allow the design and adaptive management of NbS to support healthy and resilient ecosystems, and thereby enhance their effectiveness for meeting both climate and biodiversity targets.

This paper proposed emotion recognition methods for consecutive facial images, and implements the inference of neural network model on a field-programmable gate array (FPGA). The proposed emotion recognition methods are based on a neural network model architecture that combines convolution neural networks (CNNs), long short-term memory (LSTM), and fully connected neural networks (FCNNs), called CLDNN or ConvLSTM-FCN. This type of neural network mod-el can analyze the local feature sequences obtained through convolution of data, making it suita-ble for processing time-series data such as consecutive facial images. In this paper, sequences of facial images are sampled from videos corresponding to various emotional state of subjects. The sampled images are then pre-processed with the processes includes facial detection, greyscale conversion, resize, and data augmentation if necessary. The 2-D CNN in ConvLSTM-FCN is used for feature extraction for these pre-processed facial images. These sequences of facial im-age features are time sequences with dependent properties between the elements within them. The LSTM is then used to model these time sequences followed by fully connected neural net-works (FCNNs) for classification. The proposed consecutive facial emotion recognition method achieves an average recognition rate of 99.51% on RAVDESS dataset, 87.80% on BAUM-1s dataset and 96.82% on eNTERFACE’05 data set, using 10-fold cross-validation on the PC. Some com-parisons of recognition accuracies between the proposed method and the other existing related works are conducted in this paper. According to the comparisons, the proposed emotion recog-nition methods outperform the existing related researches. The proposed emotion recognition methods are then implemented on an FPGA chip using the neural network model inference algo-rithms in this paper, and the accuracies of the experiments conducted on the FPGA chip are iden-tical to those obtained on the PC. This verifies that the proposed neural network model imple-mented on the FPGA chip performs well.

Elliptic curve cryptography (ECC) over prime fields relies on scalar point multiplication realized by point addition and point doubling. Point addition and point doubling operations consist of many modular multiplications of large operands (256 bits for example), especially in projective and Jacobian coordinates which eliminate the modular inversion required in affine coordinates for every point addition or point doubling operation. Accelerating modular multiplication is therefore important for high-performance ECC. This paper presents the hardware implementations of modular multiplication algorithms, including 1) Interleaved modular multiplication (IMM), 2) Montgomery modular multiplication (MMM), 3) Shift-sub modular multiplication (SSMM), 4) SSMM with advance preparation (SSMMPRE), and 5) SSMM with CSAs and sign detection (SSMMCSA) algorithms, and evaluates their execution time (the number of clock cycles and clock frequency) and required hardware resources (ALMs and registers). Experimental results show that SSMM is 1.76 times faster than IMM, and SSMMCSA is 3.21 times faster than IMM. We also present the ECC hardware implementations based on the Secp256k1 protocol in affine, projective, and Jacobian coordinates using the IMM, SSMM, SSMMPRE, and SSMMCSA algorithms, and investigate their cost and performance. Our ECC implementations can be applied to the design of hardware security module systems.

Internet of thing (IoT) has been used in different aspect of life as industry, and daily life. Aligned with IoT, Quantum computers have been generated with high features that can accomplish complicated tasks with high speed. IoT and Quantum computers don’t match in resources and due to this collaboration between the two terms, it was found there are many challenges with quantum computers brought some security concerns. This paper will examine all challenges and future direction that face the use of IoT through using different quantum cryptograph methods. The first part on the paper discussed the vulnerabilities of existing cryptographic methods like RSA and ECC. these two methods were used as basic level for IoT security protocols. These cryptographic algorithms could be easily attacked by quantum computers so to ensure that IoT devices are secure must develop quantum resistant cryptographic algorithms. Next this paper will examine the challenges in implementing quantum resistant cryptographic algorithm in any IoT device through quantum resistant cryptographic algorithms such as lattice-based cryptography, code-based cryptography, multivariate cryptography, and hash-based signatures. Then, the paper discussed the future direction of securing IoT in quantum computing. In conclusion, securing IoT devices in quantum presents many challenges that require to be addressed where quantum resistant algorithms can be a solution that mitigate threats.

Due to their increased surface area, extent of swelling and active substance loading capacity and flexibility, nanogels made from natural and synthetic polymers have gained significant interest in the scientific and industrial areas. Especially, customized design and implementation of non-toxic, biocompatible, and biodegradable micro/nano carriers makes their usage very feasible for a range of biomedical applications, including drug delivery, tissue engineering, and bioimaging. The design and application methodologies of nanogels have been outlined in this review. Additionally, the most recent advancements in nanogel biomedical applications have been discussed, with a particular emphasis on applications for the delivery of drugs and biomolecules.

Vision-based tactile sensors (VBTS) have become the de facto method of giving robots the ability to obtain tactile feedback from their environment. Unlike other solutions to tactile sensing, VBTS offers high spatial resolution feedback without compromising on instrumentation costs or incurring additional maintenance expenses. However, conventional cameras used in VBTS have a fixed update rate and output redundant data, leading to computational overhead downstream. In this work, we present a neuromorphic vision-based tactile sensor (N-VBTS) that employs observations from an event-based camera for contact angle prediction. Particularly, we design and develop a novel graph neural network, dubbed TactiGraph, that asynchronously operates on graphs constructed from raw N-VBTS streams exploiting their spatiotemporal correlations to perform predictions. Although conventional VBTS uses an internal illumination source, TactiGraph is reported to perform efficiently in both scenarios, with and without an internal illumination source. Rigorous experimental results revealed that TactiGraph achieved a mean absolute error of 0.62∘ in predicting the contact angle and was faster and more efficient than both conventional VBTS and other N-VBTS, with lower instrumentation costs. Specifically, N-VBTS requires only 5.5% of the compute-time needed by VBTS when both are tested on the same scenario.

For disciplines like biological science, security, and the medical field, link prediction is a popular research area. To demonstrate the link prediction many methods have been proposed. Some of them that have been demonstrated through this review paper are TransE, Complex, DistMult, and DensE models. Each model defines link prediction with different perceptions. We argue that the practical performance potential of these methods, having similar parameter values, using the fine-tuning technique to evaluate their reliability and reproducibility of results. We describe those methods and experiments; provide theoretical proofs and experimental examples, demonstrating how current link prediction methods work in such settings. We use the standard evaluation metrics for testing the model's ability.

Zoos are increasingly putting in place formalized animal welfare assessment programs to allow monitoring of welfare over time, as well as to aid in resource prioritization. These programs tend to rely on assessment tools that incorporate resource-based and observational animal- focused measures since it is rarely feasible to obtain measures of physiology in zoo-housed animals. A range of assessment tools are available which commonly have a basis in the Five Domains framework. A comprehensive review of the literature was conducted to bring together recent studies examining welfare assessment methods in zoo animals. A summary of these methods is provided with advantages and limitations of the approach es presented. We then highlight practical considerations with respect to implementation of these tools into practice, for example scoring schemes, weighting of criteria, and innate animal factors for consideration. It is concluded that would be value in standardizing guidelines for development of welfare assessment tools since zoo accreditation bodies rarely prescribe these. There is also a need to develop taxon or species- specific assessment tools to inform welfare management.

Iterative Stochastic decoding is an alternative to standard fixed-point decoding of Low-density parity check codes (LDPC) to reduce inter-node routing. In this paper, we propose a Flexible Field-Programmable Gate Array (FPGA)-Based Stochastic decoding (SD) hardware architecture for LDPC codes in the Fifth-Generation (5G) New Radio (NR) Standard that supports decoding of set of various code rates. This decoder’s runtime flexibility is desirable to switch a better performing code rate automatically based on the channel conditions without the extra time needed for reprogramming of FPGA. An offline design method is implemented to generate the hardware description language (HDL) code description of the decoder for the required code-rate set, which is further synthesized and integrated into the Xilinx Kintex-7 series FPGA board to determine the hardware resource utilisation and processing throughput. The Synopsys design tools were employed during both the simulation and synthesis stages, in combination with TSMC 65-nm CMOS standard cell technology, to facilitate comparative analysis. Compared with state-of-the-art designs, the proposed architecture reduces hardware utilization by up to 26% and achieved energy efficiency by 52%.

The augmenting commitment in the entrepreneurial learning process, both at academic and industry level, has led to new mechanisms and methodologies. Entrepreneurship literature has shown evidence of raising interest in the problem-based learning (PBL) methodology with regard to upcoming events from the surrounding learning context. This paper presents a Systematic Bibliographic Literature Review (SBLR) with respect to the application of PBL throughout distinct entrepreneurial processes either in higher education, or in industry. It aimed to identify relevant entrepreneurial opportunities for PBL. Bibliographic databases were searched for documents published between 2002 and May 2024 to categorize key topics discussed in the literature on PBL and entrepreneurship. The review process identified 142 empirical and non-empirical papers on entrepreneurship related PBL. Data analysis revealed diverse subthemes for PBL uses in entrepreneurship in both higher education institutions and industry. The research questions “What is the interplay of problem-based learning methodology with entrepreneurship?” guided the study. The central output of the research is the discovery of the varying uses of PBL to cope with diverse events arising within entrepreneurship context. Future research directions are suggested.

Herein we report the expansion of the chemical space available from the chitin, accessible via the biogenic N-platforms 3A5AF, M4A2C and di-HAF. The biologically active heteroaromatics furo[3,2-d]pyrimidin-4-one and furo[3,2-d]pyrimidin-4-amine can be selectively accessed from 3A5AF and M4A2C, respectively. The chiral pool synthon di-HAF is a viable substrate for the Achmatowicz rearrangement, providing streamlined access to 2-aminosugars possessing a versatile hydroxymethyl group at C5.

Human induced climate change led to the recognition of Community-Based Adaptation (CBA) as one of the remedies in building adaptive capacity and resilience of communities. It recognizes the agency of communities in shaping the optimal strategy. CBA interventions are vital in addressing community needs and contextual specificities, enable participatory and inclusive engagement and thereby facilitate more profound adaptation impacts. Agent-based modelling (ABM) has the potential to be an invaluable approach in developing tailored adaptation strategies considering capacities, resources, skills, priorities, needs and the cultural context of local communities. ABM allows to capture the complex relationships among various components within community decision making on CBA actions, the CBA actions themselves and the environment, however available tools provide for various degrees of freedom in agent definition, sensitivity analysis, scalability, experiment design and output analysis to name a few. This article assesses all available ABM modelling and simulation tools for its application in the context of CBA. NetLogo emerges as the most suitable tool for incorporating and handling the special features of CBA. It is closely followed by GAMA and Envision. The article provides insights and guidance to researchers and practitioners in selecting ABM tools aligned with the specific requirements of their CBA simulations and projects.

Due to the rapid growth of the Internet of Things (IoT), securing communications between a huge number of devices has become very difficult. Access controls and authentication secure the connection between IoT devices and protect sensitive data from unauthorized users or malicious attackers. In this paper, we provide a comprehensive review to emphasize the critical role of authentication and access control in securing IoT environments. This paper explores different types of access controls, like Attribute-Based Access Control and Role-Based Access Control. Furthermore, it demonstrates different authentication techniques, like passwords and biometrics. Based on the previous mechanisms, we discuss different IoT security challenges regarding authentication and access control mechanisms and highlight future directions. In addition, this paper investigates the integration between access control and authentication to safeguard IoT communications.

The evolution of photovoltaic cells is intrinsically linked to advancements in the materials from which they are fabricated. This review paper provides an in-depth analysis of the latest developments in silicon-based, organic, and perovskite solar cells, which are at the forefront of photovoltaic research. We scrutinize the unique characteristics, advantages, and limitations of each material class, emphasizing their contributions to efficiency, stability, and commercial viability. Silicon-based cells are explored for their enduring relevance and recent innovations in crystalline structures. Organic photovoltaic cells are examined for their flexibility and potential for low-cost production, while perovskites are highlighted for their remarkable efficiency gains and ease of fabrication. The paper also addresses the challenges of material stability, scalability, and environmental impact, offering a balanced perspective on the current state and future potential of these material technologies.

The aim of this study was to investigate the impact of Process Oriented Guided Inquiry Learning (POGIL)-based instruction versus lecture-based instruction on Grade 12 students’ performance in circular motion unit. A quasi-experimental, pretest-posttest design, the impact of POGIL-based instruction versus lecture-based instruction on students’ performance as measured by three types of cognitive outcomes: Knowing, Applying and Reasoning (KAR). The total number of participants was approximately 110 students (N=110); 54 were assigned to treatment groups (25 girls and 29 boys) and 56 were assigned to control groups (27 girls and 29 boys). The treatment group was taught a unit of circular motion in physics using POGIL-based instruction while the control group was taught the unit using lecture-based instruction. The findings of the study showed statistically significant differences between students of the control group and the treatment group in favor of the later regarding their circular motion performance, suggesting the superiority of the POGIL in enhancing student understanding of the circular motion.

This article investigates the prospect of implementing multidisciplinary and multicultural student teamwork (MMT) involving Case-based Learning (CBL) and Problem-based Learning (PBL) as a sustainable teaching practice. Based on a mixed methods approach, which includes direct observation (both physical and virtual), questionnaire distribution and focus-group interviews the study reveals that MMT through CBL and PBL can both facilitate and hinder sustainable learning. Our findings show that while MMT enhances knowledge sharing, it also poses a wide range of challenges, raising questions about its social significance as a sustainable teaching practice. The study suggests the implementation of certain mechanisms, such as ‘Teamwork Training’ and ‘Pedagogical Mentors’, aiming to strengthen the sustainable orientation of MMT through CBL and PBL.

In MBSE there is yet no converged terminology. The term ’system model’ is used in different contexts in literature. In this study we elaborated the definitions and usages of the term ’system model’, to find a common definition. 104 publications have been analyzed in depth for their usage and definition as well as their meta-data e.g., the publication year and publication background to find some common patterns. While the term is gaining more interest in recent years it is used in a broad range of contexts for both analytical and synthetic use cases. Based on this three categories of system models have been defined and integrated into a more precise definition.

This article discusses the use of game design as a method for interdisciplinary project-based teaching in secondary school education to convey informatics and society topics. There is a lot of knowledge about learning games but little background on project-based teaching using game design as a method. We present the results of an analysis of student-created games and an evaluation of a student-authored database on learning contents found in commercial off-the-shelf games. We further contextualise these findings using a group discussion with teachers. Results underline the effectiveness of project-based teaching to raise awareness for informatics and society topics. We further outline informatics and society topics that are particularly interesting to students, genre preferences and potentially engaging game mechanics stemming from our analyses.

The ubiquity of mobile sensors (such as GPS, accelerometer and gyroscope) together with increasing computational power have enabled an easier access to contextual information, which proved its value in next generation of the recommender applications. The importance of contextual information has been recognized by researchers in many disciplines, such as ubiquitous and mobile computing, to filter the query results and provide recommendations based on different user status. A context-aware recommendation system (CoARS) provides a personalized service to each individual user, driven by his or her particular needs and interests at any location and anytime. Therefore, a contextual recommendation system changes in real time as a user’s circumstances changes. CoARS is one of the major applications that has been refined over the years due to the evolving geospatial techniques and big data management practices. In this paper, a CoARS is designed and implemented to combine the context information from smartphones’ sensors and user preferences to improve efficiency and usability of the recommendation. The proposed approach combines user’s context information (such as location, time, and transportation mode), personalized preferences (using individuals past behavior), and item-based recommendations (such as item’s ranking and type) to personally filter the item list. The context-aware methodology is based on preprocessing and filtering of raw data, context extraction and context reasoning. This study examined the application of such a system in recommending a suitable restaurant using both web-based and android platforms. The implemented system uses CoARS techniques to provide beneficial and accurate recommendations to the users. The capabilities of the system is evaluated successfully with recommendation experiment and usability test.

Hospital-based programs democratize mRNA therapeutics by facilitating the processes to translate a novel RNA idea from the bench to the clinic. Because mRNA is essentially biological software, therapeutic RNA constructs can be rapidly developed. The generation of small batches of clinical grade mRNA to support IND applications and first-in-man clinical trials, as well as personalized mRNA therapeutics delivered at the point-of-care, is feasible at a modest scale of cGMP manufacturing. Advances in mRNA manufacturing science and innovations in mRNA biology, are increasing the scope of mRNA clinical applications.

Exploring new approaches to innovating higher vocational education is a worldwide pursuit driven by the increasing demand for graduates equipped with competencies. This study investigated how Outcomes-Based Education (OBE) influences the attainment of graduate competence (AGC) in China’s higher vocational education, using the theory of Constructive Alignment (CA) as its foundation. The OBE framework incorporates intended learning outcomes (ILOs), project-based learning (PjBL), assessment strategies (ASs), and AGC. The study tested the model by assessing the impact of ILOs, PjBL, and ASs on AGC, respectively and sequentially. Surveys were administered to 320 CBEC learners in April 2024, resulting in 301 usable responses. Data were analyzed using structural equation modeling (SEM) with SPSS 23.0 and AMOS 24.0. Results indicated that PjBL and ASs were directly and positively related to graduate competency attainment, while ILOs were indirectly associated with graduate competence through the mediating roles of PjBL and ASs. The most substantial mediating effect between ILOs and graduate competence was ASs, followed by PjBL, and then, the chain mediating effect of PjBL and ASs. These findings enhance the theoretical understanding of OBE and provide detailed procedures for tracking and enhancing sustainability in higher vocational education. Beneficiaries include educators, policymakers, and accreditation bodies.

Modern fighter aircraft increasingly need to conjugate aerodynamic performance and low observability. In this paper we showcase a methodology for a gradient-based bidisciplinary aero-stealth optimization. The shape of the aircraft is parametrized with the help of a CAD modeler, and we optimize with the SLSQP algorithm. The drag, computed with the help of a RANS method, is used as the aerodynamic criterion. The stealth criterion, a function is derived from the radar cross section in a given cone of directions, weighed with a function whose goal is to cancel the electromagnetic intensity in a given direction. Stealth is achieved passively by scattering back the electromagnetic energy away from the radar antenna and no energy is absorbed by the aircraft, which is considered as a perfect conductor. A Pareto front is identified by varying the weights of the aerodynamic and stealth criteria. The Pareto front allows for an easy identification of the CAD model corresponding to a chosen aero-stealth trade-off.

Drug discovery utilizes high-throughput screening (HTS) methods applying target and cell-based assays. This review discusses the challenges and benefits associated with these assays in HTS. Discussed the strategies that can be applied for the development of screening assays through primary and secondary screens for target identification. Further discussion on identify-ing the most efficacious drugs following these approaches in cancer. Even though various drugs have been identified to treat cancer, there is high demand of more relevant phenotypic assays to produce desired diseased phenotype to only highlighting the specific targets instead of off-targets. Hopefully, the new developing strategies could provide innovative drugs to treat cancer patients to reduce mortality rate.

The correlations of seismic noise, recorded during 1997-2022 at 229 stations around the world are investigated. The property of waveforms, known as the Donoho-Johnston threshold, is analyzed, which separates the absolute values of the orthogonal wavelet coefficients into "small" and "large". Network of 50 reference points is considered. For each reference point, a time series with a time step of 1 day is calculated as the median of the values of the DJ index from the 5 nearest stations. For each reference point, the correlations between the values of the DJ index at other reference points are calculated in a sliding time window of 365 days. Average values of the DJ index decrease, which is interpreted as indicators of global seismic hazard increasing. The maximum distances between reference points with strong correlations show an explosive increase after 2011. Bursts in the mean coherences between the length of day (LOD) and the values of the DJ index at the reference points precede the release of seismic energy with a delay of about 530 days. High amplitude of the DJ index response to LOD for the times 2020-2022 was identified, which may forecast a strong earthquake in the second half of 2023.

Noise in requirements has been known to be a defect in software requirements specifications (SRS). Detecting defects at an early stage is crucial in the process of software development. Noise can be in the form of irrelevant requirements that are included within a SRS. A previous study had attempted to detect noise in SRS, in which noise was considered as an outlier. However, the resulting method only demonstrated a moderate reliability due to the overshadowing of unique actor words by unique action words in the topic-word distribution. In this study, we propose a framework to identify irrelevant requirements based on the MultiPhiLDA method. The proposed framework distinguishes the topic-word distribution of actor words and action words as two separate topic-word distributions with two multinomial probability functions. Weights are used to maintain a proportional contribution of actor and action words. We also explore the use of two outlier detection methods, namely Percentile-based Outlier Detection (PBOD) and Angle-based Outlier Detection (ABOD), to distinguish irrelevant requirements from relevant requirements. The experimental results show that the proposed framework was able to exhibit better performance than previous methods. Furthermore, the use of the combination of ABOD as the outlier detection method and topic coherence as the estimation approach to determine the optimal number of topics and iterations in the proposed framework outperformed the other combinations and obtained sensitivity, specificity, F1-score, and G-mean values of 0.59, 0.65, 0.62, and 0.62, respectively.

Animal-based measures are the measure of choice in animal welfare assessment protocols as they can often be applied completely independently to the housing or production system employed. Although there has been a small body of work on potential animal-based measures for farmed crocodilians [1-3], they have not been studied in the context of an animal welfare assessment protocol. Potential animal-based measures, that could be used to reflect the welfare state of farmed crocodilians, were identified and aligned with the Welfare Quality® principles of good housing, good health, good feeding and appropriate behaviour. A consultation process with a panel of experts was used to evaluate and score the potential measures in terms of validity and feasibility. This resulted in a toolbox of measures being identified for further development and integration into animal welfare assessment on the farm. Animal-based measures related to ‘good feeding’ and ‘good health’ received the highest scores for validity and feasibility by the experts. There was less agreement on the animal-based measures that could be used to reflect ‘appropriate behaviour’. Where no animal-based measures were deemed to reliably reflect a welfare criterion nor be useful as a measure on the farm, additional measures of resources or management were suggested as alternatives. Future work in this area should focus on the reliability of the proposed measures and involve further evaluation of their validity and feasibility as they relate to different species of crocodilian and farming system.

The exploitation of lipid membranes in biosensors has provided the ability to reconstitute a considerable part of their functionality to detect trace of food toxicants and environmental pollutants. Nanotechnology enabled sensor miniaturization and extended the range of biological moieties that could be immobilized within a lipid bilayer device. This chapter reviews recent progress in biosensor technologies based on lipid membranes suitable for environmental applications and food quality monitoring. Numerous biosensing applications are presented, putting emphasis on novel systems, new sensing techniques and nanotechnology-based transduction schemes. The range of analytes that can be currently detected include, insecticides, pesticides, herbicides, metals, toxins, antibiotics, microorganisms, hormones, dioxins, etc. Technology limitations and future prospects are discussed, focused on the evaluation/ validation and eventually commercialization of the proposed sensors.

The exploitation of lipid membranes in biosensors has provided the ability to reconstitute a considerable part of their functionality to detect trace of food toxicants and environmental pollutants. Nanotechnology enabled sensor miniaturization and extended the range of biological moieties that could be immobilized within a lipid bilayer device. This chapter reviews recent progress in biosensor technologies based on lipid membranes suitable for environmental applications and food quality monitoring. Numerous biosensing applications are presented, putting emphasis on novel systems, new sensing techniques and nanotechnology-based transduction schemes. The range of analytes that can be currently detected include, insecticides, pesticides, herbicides, metals, toxins, antibiotics, microorganisms, hormones, dioxins, etc. Technology limitations and future prospects are discussed, focused on the evaluation/ validation and eventually commercialization of the proposed sensors.

Given the increase in consumers’ preferences for coffee, it is becoming important to understand their decision-making processes in the coffee chain context. To deepen the understanding of sustainable outcomes in this context, this study investigates the role of dedication- and constraint-based mechanisms in forming consumers’ repurchase and positive word-of-mouth (WOM) intentions, two critical sustainable outcomes. We examined the effects of coffee quality, the quality of the physical environment, and service quality in accelerating the formation of dedication-based factors. Moreover, this study offers an in-depth understanding of the enablers of perceived switching costs. Data collected from 238 university students that frequently visit coffee chains are empirically tested against the proposed theoretical framework by using structural equation modeling. The results confirm that both dedication- and constraint-based factors substantially predict consumers’ sustainable outcomes in the coffee chain context. Brand image and perceived switching costs play an important role in enhancing consumers’ repurchase and positive WOM intentions compared with customer satisfaction. Coffee quality is significantly associated with both customer satisfaction and brand image, whereas the quality of the physical environment and service quality are only significantly associated with brand image. Habit is found to be the key enabler of perceived switching costs, while loyalty programs have no significant impact on perceived switching costs.

Effectively mapping and monitoring rubber plantation is still changing. Previous studies have explored the potential of phenology features for rubber plantation mapping through a pixel-based approach (pixel-based phenology approach). However, in fragmented mountainous Xishuangbanna, it could lead to noises and low accuracy of resultant maps. In this study, we investigated the capability of an integrated approach by combining phenology information with an object-based approach (object-based phenology approach) to map rubber plantations in Xishuangbanna. Moderate Resolution Imaging Spectroradiometer (MODIS) data were firstly used to acquire the temporal profile and phenological features of rubber plantations and natural forests, which delineates the time windows of defoliation and foliation phases. Landsat images were then used to extract a phenology algorithm comparing three different approaches: pixel-based phenology, object-based phenology, and extended object-based phenology to separate rubber plantations and natural forests. The results showed that the two object-based approaches achieved higher accuracy than the pixel-based approach, having overall accuracies of 96.4%, 97.4%, and 95.5%, respectively. This study proved the reliability of a phenology-based rubber mapping in fragmented landscapes with a distinct dry/cool season using Landsat images. This study indicated that the object-based phenology approaches can effectively improve the accuracy of the resultant maps in fragmented landscapes.

Saudi Arabia is an oil-reliant nation as a large percentage of its GDP comes from oil resources. Oil dependency leaves a county at the mercy of the international crude market, and a decrease in the price of crude can seriously destabilize the economy of such nations. An example is the case of Venezuela whose dependence on oil caused a national disaster (McCarthy, 2017). As such, the nation’s exports, GDP, and government revenue are primarily dependent on oil revenue, and the recent decrease in the oil prices has decreased Venezuela’s national revenue resulting in economic collapse as well as inflation. A shift from a resource based economy to a knowledge based economy will help Saudi Arabia become less reliant on its oil revenues for its economic stability and growth (Nurunnabi, 2017).

The ASEAN Community-based Tourism (CBT) Standard has been adopted by 10 ASEAN member states in 2016 in order to collectively promote ASEAN as a competitive community-based tourism destination. Among the ASEAN member states, Lao PDR (Laos), has a unique CBT development experience through collaboration with various international development agencies. Such history has brought about issues when ASEAN CBT Standard was implemented at to provincial and district levels in Laos, including concerns of related communities on the Standard being not easily applicable considering the state of tourism development. While the application of the regional standard is a significant issue to the tourism industries in the Member States, however, there has been a lack of studies regarding the dynamics of implementation of regional tourism standards at the national level. In order to fill the research gap, this study utilized in-depth interviews with seven executives with significant experiences from the government, international development agency, international organization, and the private sector. Interviewees projected a diversity of perspectives on enabling factors and challenges in implementing ASEAN Community-based Tourism Standard at the national level focusing on Laos, which showed the complexity of CBT dynamics. The results also revealed how regional standards can be further recognized and promoted to the key stakeholders of Laos, better accepted and utilized by end users, and possibly better customized according to the local circumstances. Findings of this study evidence that collaboration among key stakeholders and the expected role of these stakeholders are critical when implementing ASEAN CBT Standard.

This study focuses on enhancing controllable fibrin-based hydrogels for tissue engineering, addressing existing weaknesses. By integrating a novel copolymer, we improve the foundation for cell-based angiogenesis with adaptable structural features. Tissue engineering often faces challenges like waste disposal and nutrient supply beyond the 200 µm diffusion limit. Angiogenesis breaks through this limitation, allowing the construction of larger constructs. Our innovative scaffold combination significantly boosts angiogenesis, resulting in longer branches and more capillary network junctions. The copolymer attached to fibrin fibers enables precise adjustment of hydrogel mechanical-dynamic properties for specific applications. Our material proves effective for angiogenesis, even under suppression factors like suramin. In our study, we prepared fibrin-based hydrogels with and without the copolymer PVP12400-co-GMA10mol%. Using a co-culture system of human umbilical vein endothelial cells (HUVEC) and mesenchymal stem cells (MSC), we analyzed angiogenetic behavior on and within the modified hydrogels. Capillary-like structures were reproducibly formed on different surfaces, demonstrating the general feasibility of three-dimensional endothelial cell networks in fibrin-based hydrogels. This highlights the biomaterial's suitability for in vitro pre-vascularization of biohybrid implants.

In this study, graphite, the most stable form of carbon, was examined for its hexagonal crystalline structure with specific dimensions (ao=2.46 Ǻ; co=6.70 Ǻ). Its framework comprises parallel carbon atom planes forming regular hexagons (side length 1.415 Ǻ) and 120° angles between adjacent atoms. Two structural variations exist: hexagonal symmetry (1-2-1-2-1-2 planes) and rhomboidal symmetry (1-2-3-1-2-3 planes). The research aimed to produce high-density graphite utilizing carbonaceous raw materials. Graphite-based materials often exhibit high porosity, necessitating additional treatments. The study successfully obtained mesophase tar pitch (yield: 45%), a pivotal raw material, and high-density graphite. The resulting graphite underwent characterization for physical properties (apparent and real density, porosity and compression strength), demonstrating conformity with existing literature data.

After the great success of Mobile wallet, the Internet of Things (IoT) leaves the door wide open for consumers to use their connected devices to access their bank accounts and perform routine banking activities from anywhere, anytime and with any device. However, consumers need to feel safe when interacting with IoT-based payment systems, and their personal information should be protected as much as possible. Unlike as usually done in the literature, in this paper, we introduce two lightweight and secure IoT-based payment protocols based on an identity-based signature scheme. We adopt a server-aided verification technique to construct the first scheme. This technique allows to outsource the heavy computation overhead on the sensor node to a cloud server while maintaining the user's privacy. The second scheme is built upon a pairing-free ECC-based security protocol to avoid the heavy computational complexity of bilinear pairing operations. The security reduction results of both schemes are held in the Random Oracle Model (ROM) under the discrete logarithm and computational Diffie-Hellman assumptions. Finally, we experimentally compare the proposed schemes against each other and against the original scheme on the most commonly used IoT devices: a smartphone, a smartwatch and the embedded device Raspberry Pi. Compared with existing schemes, our proposed schemes achieve significant efficiency in the term of communication and computational overheads

The complexity of modern power grids, exacerbated by integrating diverse energy sources, espe-cially inverter-based resources (IBRs), presents a significant challenge to grid operation and plan-ning since linear models fail to capture the intricate IBR dynamics. This study employs the Sparse Identification of Nonlinear Dynamics (SINDy) method to bridge the gap between theoretical un-derstanding and practical implementation in power system analysis. It introduces the novel Volterra-based Nonlinearity Index (VNI) to examine system-level nonlinearity comprehensively. The distinction of dynamics into first-order linearizable terms, second-order nonlinear dynamics, and third-order noise elucidates the intricacy of power systems. The findings demonstrate a fundamental shift in system dynamics as power sources transit to IBRs, revealing system-level nonlinearity compared to module-level nonlinearity in conventional syn-chronous generators. The VNI quantifies nonlinear-to-linear relationships, enriching our comprehension of power system behavior and offering a versatile tool for distinguishing between different nonlinearities and visualizing their distinct patterns through the proposed VIN profile.

This work aims to explore the impact of side loads, drill-pipe tool-joint (DP-TJ) speed (RPM), and mud type on the austenitic stainless steel SM2535-110 casing wear characteristics. Actual field drill pipe tool joints, casings, and drilling muds are used in this study. The results of the study show that under both types of lubrication, the wear volume increased with radial load and DP-TJ speed. SM2535-110 casing specimens tested under oil-based mud (OBM) lubrication had higher casing wear volumes than those obtained under water-based mud (WBM) lubrication. This unexpected behavior is mainly due to the increase in the surface hardness of the casing specimens tested under WBM. The results also show that the specific wear factor (K) values of specimens tested under WBM are in general 2 to 4 times higher than those obtained under OBM. While K values under WBM increase with both the side load and RPM, those under OBM show a sharp decrease with RPM. This behavior under OBM is due to this lubricant’s higher viscosity and the change of lubrication regime from thin film to thick film lubrication at higher RPM. Scanning electron microscopy (SEM) and the digital microscopic imaging (DMI) of SM235-110 casing specimens show that an aggressive combination of adhesive, abrasive, and plastic deformation was observed under WBM, while the dominant wear mechanism under OBM is abrasive wear.

Financial markets require a great deal of decision making from the investors and market makers. One metric that can help ease the process of decision making is investment risk which can be measured in two parts; systematic risk and idiosyncratic risk. Clear understanding of the volatilities in each risk component can be a powerful signal in recognizing the right assets to maximize the investment returns. In this paper, we focus on the idiosyncratic volatility values and pre-calculate the idiosyncratic volatility values for 31,198 members of NYSE, Amex and Nasdaq markets for the trades occurring between January 1963 and December 2019. Utilizing a subset of dataset, limited to Nasdaq100 index, we consider the application of machine learning techniques in predicting the idiosyncratic volatility values using the raw trade data to explore a data extension option for the future market trade records that have not yet occurred. We offer a deep learning based regression model and compare it with traditional tree-based methods on a small subset of our per-calculated idiosyncratic volatility dataset. Our analytical results show that the performance of the deep learning techniques is much more robust in comparison to that of the traditional tree-based baselines.

This study compares the effects of lecture-based instruction and process-oriented guided inquiry learning (POGIL)-based instruction on the self-efficacy performance of Grade 12 students. A quasi-experimental, pretest-posttest design was adopted to investigate and assess the impact of POGIL-based instruction versus lecture-based instruction on students’ performance as measured by three types of cognitive outcomes; Knowing, Applying and Reasoning (KAR). Two government high schools in Alain were selected as research sites, one for the boys and one for the girls. The total number of participants was approximately 110 students (N=110); 54 were assigned to treatment groups (25 girls and 29 boys), and 56 were assigned to control groups (27 girls and 29 boys). The treatment group was taught a circular motion unit in physics using POGIL-based instruction, while the control group was taught the unit using lecture-based instruction. The study's findings showed statistically significant differences between students of the control group and the treatment group in favour of the latter regarding their science performance, self-efficacy and science-related attitudes. Moreover, positive correlations were found between participants’ performance at the KAR test, self-efficacy and scientific attitudes towards scientific inquiry after the intervention. In conclusion, it is recommended to shift teaching towards POGIL-based instruction due to its positive impact on students’ performance and self-efficacy. It is also suggested to replicate the study to include government and private schools, elementary and high schools, teachers and advisors.

The production of public goods is a necessary condition for the survival of the species but it comes at the expense of individual growth. In a prototype bacterial colony, we model the role of quorum sensing as a resource redistribution mechanism. Two types of bacterial colonies are analyzed, one made up of a single strain and one made up of two different strains. Based on a recent series of experimental data present in the literature, we analyze two types of strains with different extinction times: strains that consume available resources very quickly, therefore becoming extinct quickly, and strains that consume resources slowly and die due to aging. We show that the proposed quorum sensing model describes the main experimental result, namely that coexistence favors the survival of both strains. Furthermore, the production of public goods is maximized when both types of individuals have the maximum proliferation output. Finally, we highlight the role played by so-called dormant cells in the duration of survival time. These cells are of particular interest, because their ability to counteract different types of stress (e.g. the use of antibiotics) still constitutes a challenge.